R&D predictability: The path to profitability
Poor schedule predictability of IC development projects is the Achilles heel of semiconductor companies. It manifests itself as high schedule slip and is among the most important R&D metrics, measuring how well project schedules reflect reality. Most don't.
Companies traditionally view schedule slip not as a result of faulty project plans, but rather as a consequence of unforeseeable perturbations occurring during the development process. The picture is incomplete and inaccurate. Slip must also be viewed through the project planning lens, because many events labeled as unforeseeable can be fully contemplated in the project plan with proper modeling. The payoff is big—reliable plans, which is the path to profitability.
To read the full article, click here
Related Semiconductor IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
- Neuromorphic Processor IP
- Lossless & Lossy Frame Compression IP
Related Blogs
- Throughput, not productivity, is what matters
- The most important R&D performance metrics
- Optimal team sizes for chip projects
- The politics of productivity
Latest Blogs
- MIPS P8700 RISC-V Processor for Advanced Functional Safety Systems
- Boost SoC Flexibility: 4 Design Tips for Memory Subsystems with Combo DDR3/4 Interfaces
- High Bandwidth Memory Evolution from First Generation HBM to the Latest HBM4
- Keeping Pace with CXL Specification Revisions
- Silicon-proven LVTS for 2nm: a new era of accuracy and integration in thermal monitoring