Boosting Data Center Performance to the Next Level with PCIe 6.0 & CXL 3.0
2022 has seen major updates to two standards critical to the future evolution of the data center: PCI Express® (PCIe®) and Compute Express Link™ (CXL™). The two are interwoven, and in this blog, we’ll look at their relationship and the impact of latest developments.
Like many standards in the computing world, PCIe has proliferated far beyond its original remit. Over the past two decades, it has become not just the de facto standard for computing connectivity, it has also expanded into new applications, such as IoT, automotive, government, and many more. With its most recent update to PCIe 6.0, it is poised to take data center performance to the next level.
PCIe 6.0 boosts signaling rates to 64 gigatransfers per second (GT/s), twice that of PCIe 5.0. Initial designs incorporating PCIe 6.0 will be where bandwidth demands are most intense right now: in the heart of the data center. For bandwidth-hungry, data-intensive workloads, the extra bandwidth offered by PCIe 6.0 will certainly be a game changer!
Related Semiconductor IP
- PCIe 6.0 PHY, TSMC N6 x2 1.2V, North/South (vertical) poly orientation
- PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation
- PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation
- PCIe 6.0 PHY, SS SF5A x4, North/South (vertical) poly orientation
- PCIe 6.0 PHY, SS SF5A x1, North/South (vertical) poly orientation
Related Blogs
- Unraveling the Newly Introduced Segmentation in PCIe 6.0
- PCIe 6.0 Address Translation Services: Verification Challenges and Strategies
- Unveiling NOP Insertion Hint: A Performance Optimizer in CXL 3.0
- Cadence support for the Open NAND Flash Interface (ONFI) 3.0 controller and PHY IP solution + PCIe Controller IP opening the door for NVM Express support
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?