Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM
Even though it's been over 2 months since this year's Design Automation Conference in San Francisco, I am still surprised by the response that metric-driven, mixed-signal verification gets from our design community. Cadence had quite a few customer presentations at the EDA360 Theater at DAC this year. However, there was one presentation titled "Metric Driven Verification Approach for Analog/Mixed Signal IPs" authored by Pierluigi Daglio and Marco Carlini from STMicroelectronics that has garnered a lot of interest from the verification community.
Metric-driven verification is the norm for digital designs. But, we can extend this concept to analog/mixed signal designs. Analog/mixed signal verification in the context of full chip verification can achieve a respectable coverage level without compromising on performance levels of digital verification. This can be accomplished by using more robust and abstract analog behavior models such as Real Number (RNM) models using Verilog-AMS wreal as an example. RNM models are also provided in VHDL and System Verilog extensions as well.
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related Blogs
- Mixed Signal Success Requires the Voice of Analog Designers
- Keeping Pace with Memory Technology using Advanced Verification
- How to Address the Top 7 JEDEC-UFS Stack Verification Challenges Using Test Suites
- Verification of the Lane Adapter FSM of a USB4 Router Design Is Not Simple
Latest Blogs
- lowRISC Tackles Post-Quantum Cryptography Challenges through Research Collaborations
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison
- Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V Power