The New MIPS - Solving Compute Where It Happens
Timing, opportunity and geographic location matter in life – when we decide to do important things and where we decide to live and work. It turns out these factors are also important in solving the biggest compute challenges our industry is facing at this time. I am personally very thankful for joining the MIPS leadership team at a pivotal time of transition and growth. There is not a better company as storied and as interesting as MIPS. Like many of you, I studied MIPS ISA in college and still am nostalgic about it. MIPS ISA based processors have powered some of the most iconic computing hardware from SGI workstations to our favorite game consoles, to the automotive systems that protect us and the networking equipment that connects us all together to this day.
RISC-V is Inevitable: Open and Modular
In 2021 when MIPS made the decision to transition from the MIPS ISA to RISC-V, this was a recognition of both the incredible cost of developing and maintaining an ecosystem around an Instruction Set Architecture (ISA) as well as the business model of RISC-V. As Calista Redmond eloquently put it, RISC-V is inevitable. Regardless of the differences between the MIPS and RISC-V architectures, both share in the philosophy that Reduced Instruction Set Computing (RISC) is the future. For those of us who lived through the early days of RISC-V, the ecosystem was a weakness. Every meeting was spent describing RISC-V and why it was significant. Ecosystem maturity was always the first customer concern. Nowadays, the script has flipped, and the established ecosystem and openness are the reasons RISC-V has become as successful as it has. When given a choice, an open ecosystem always wins… Just ask the Linux folks. That is not to say that RISC-V has more market share than incumbents in every market, but the inertia at this point is unstoppable. One thing the RISC-V ISA does very well is its modular approach to the architecture. Instruction extensions build on top of each other and allow for specialization without sacrificing ecosystem compatibility. This is a key feature/capability that MIPS plans to make use of.
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Related Semiconductor IP
- RISC-V CPU IP
- RISC-V Vector Extension
- RISC-V Real-time Processor
- RISC-V High Performance Processor
- 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
Related Blogs
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Scaling Out Deep Learning (DL) Inference and Training: Addressing Bottlenecks with Storage, Networking with RISC-V CPUs
- The Shift-Left Approach to Software Development