Are low power and FPGA an oxymoron?
There is a lot of talk about low power these days, and not surprising given the way that handheld devices are become the must have things to be seen with, play with, and to keep our productivity high.
Power has become one of the principle attributes that designs are optimized for. We see power optimization techniques popping up at all abstraction levels of the design, from a new fabrication technology that reduces transistor leakage, through clock gating, power gating, variable voltage and frequency and everything in between.
The other day I wrote a blog that talked about the differences between accuracy and fidelity when it comes to power estimation. Accuracy can only come with detail, but detail often prevents our ability to access the information from which we can make other important decisions. When we cannot have accuracy, we need fidelity.
To read the full article, click here
Related Semiconductor IP
- xSPI Multiple Bus Memory Controller
- MIPI CSI-2 IP
- PCIe Gen 7 Verification IP
- WIFI 2.4G/5G Low Power Wakeup Radio IP
- Radar IP
Related Blogs
- 28nm-SLP technology - The Superior Low Power, GHz Class Mobile Solution
- Cadence PCIe Solutions: Configurable, Compliant, and Low Power
- NoC 102: Using SonicsGN to Address Low Power Requirements From IoT to Servers
- Is Low Power a Challenge? ICE-Grain Answers the Challenge
Latest Blogs
- The Growing Importance of PVT Monitoring for Silicon Lifecycle Management
- Unlock early software development for custom RISC-V designs with faster simulation
- HBM4 Boosts Memory Performance for AI Training
- Using AI to Accelerate Chip Design: Dynamic, Adaptive Flows
- Locking When Emulating Xtensa LX Multi-Core on a Xilinx FPGA