IEDM: TSMC N3 Details
January 25, 2023
As you know from previous blog posts, I attended IEDM in San Francisco in December. There were two presentations about TSMC's N3 process. This is actually a bit of a misnomer since TSMC has two N3 processes, one simply called N3. The other (the second generation) is called N3E.
To read the full article, click here
Related Semiconductor IP
- Voltage Monitor with Digital Output (Multi-domain supply monitoring), TSMC N3
- Thermal Diode with Base Pin, TSMC N3
- Temperature Sensor Non-Deep NWELL, TSMC N3
- Temperature Sensor Deep NWELL, TSMC N3
- Distributed Thermal Sensor (DTS) Non-Deep NWELL, TSMC N3
Related Blogs
- IEDM: TSMC on 3nm Device Options
- TSMC N3 will be a Record Setting Node!
- Synopsys Accelerates Multi-Die System Designs With Successful UCIe PHY IP Tape-Out on TSMC N3E Process
- Synopsys Tapes Out SLM PVT Monitor IP on TSMC N5 and N3E Processes
Latest Blogs
- MIPS P8700 RISC-V Processor for Advanced Functional Safety Systems
- Boost SoC Flexibility: 4 Design Tips for Memory Subsystems with Combo DDR3/4 Interfaces
- High Bandwidth Memory Evolution from First Generation HBM to the Latest HBM4
- Keeping Pace with CXL Specification Revisions
- Silicon-proven LVTS for 2nm: a new era of accuracy and integration in thermal monitoring