TSMC N3 will be a Record Setting Node!
With the TSMC Technical Symposium coming next month there is quite a bit of excitement inside the fabless semiconductor ecosystem. Not only will TSMC give an update on N3, we should also hear details of the upcoming N2 process.
Hopefully TSMC will again share the number of tape-outs confirmed for their latest process node. Given what I have heard inside the ecosystem, N3 tape-outs will be at a record setting number. Not only has Intel joined TSMC for multi-product high volume N3 production, it has been reported that Qualcomm and Nvidia will also use N3 for their leading edge SoCs and GPUs. In fact, it would be easier to list the companies that will not use TSMC for 3nm but at this point I don’t know of any. It is very clear that TSMC has won the FinFET battle by a very large margin, absolutely.
To read the full article, click here
Related Semiconductor IP
- USB 2.0 femtoPHY -TSMC N6 18 x1, OTG, North/South (vertical) poly orientation
- USB 2.0 femtoPHY - TSMC N5 12 x1, North/South (vertical) poly orientation
- USB 2.0 femtoPHY - TSMC N3P 1.2V x1, North/South (vertical) poly orientation
- USB 2.0 picoPHY - TSMC 90LPFS33 x1, OTG
- USB 2.0 femtoPHY - TSMC 7FF18 x1, OTG, North/South (vertical) poly orientation
Related Blogs
- IEDM: TSMC N3 Details
- Synopsys Accelerates Multi-Die System Designs With Successful UCIe PHY IP Tape-Out on TSMC N3E Process
- Synopsys Tapes Out SLM PVT Monitor IP on TSMC N5 and N3E Processes
- TSMC 28nm Beats Q1 2012 Expectations!
Latest Blogs
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits
- eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview