Arteris × XuanTie: The “Data Highway” for High-Performance RISC-V SoCs

By Arteris

March 30, 2026

On March 24, the 2026 XuanTie RISC-V Ecosystem Conference, hosted by Alibaba DAMO Academy, was held in Shanghai. Hundreds of industry and academic institutions from around the world—including Qualcomm, Arteris, Canonical, SHD Group, Haier, and ZTE—gathered to share cutting-edge practices in RISC-V. As a key member of the Wujian Alliance, Arteris maintains a deep strategic partnership with the DAMO Academy XuanTie team, with both parties committed to providing high-performance, reusable system IP solutions for the RISC-V ecosystem.

At the conference, Alibaba DAMO Academy unveiled the XuanTie C950, a high-performance RISC-V CPU that sets a new global performance record, and launched two RISC-V-native AI engines to accelerate the integration of high-performance general-purpose computing with AI computing. Academician Ni Guangnan of the Chinese Academy of Engineering stated at the event: “In the fifteen years since its inception, RISC-V has followed a remarkable path of rapid development, rapidly moving from a ‘backup option’ to the ‘mainstream.'”

At this annual flagship event for the RISC-V ecosystem, K. Charles Janac, President and CEO of Arteris, was invited to speak. His presentation addressed the most critical yet often overlooked aspect of chip design—data movement.

The Three Core Functions of Semiconductor Chips: Compute, Store, Move

In his speech, Charlie pointed out that semiconductor chips have three core functions:

• Processors handle data processing/compute
• Memory handles data storage
• Network-on-Chip (NoC) handles data movement

All three are indispensable. However, much of the industry’s focus tends to be on the first two, while the efficiency of data movement within the chip often becomes the performance bottleneck.

“Optimizing data movement directly determines a chip’s functionality, performance, and power efficiency,” Charlie said.

And this is precisely the area where Arteris has been deeply involved for many years.

Collaboration with XuanTie: Ncore Takes Center Stage, Building a Complete System IP Matrix

Arteris’ collaboration with XuanTie goes far beyond simple compatibility with a single product. The architecture diagram Charlie presented in his speech clearly illustrated this: the Ncore cache-coherent NoC IP is at the center of this partnership—it handles efficient communication between the multi-core CPU cluster, system-level cache, and memory controller, ensuring smooth data flow across multiple cores.

On top of Ncore, Arteris provides complete system IP support for the XuanTie ecosystem:

• Flex Family (FlexGen/FlexNoC/FlexWay) of NoC IPs serves as non-coherent interconnect IP, connecting PCIe, DDR controllers, wireless communication, functional safety modules, display interfaces, and other peripherals
• CodaCache acts as the last-level cache, effectively reducing access latency to main memory
• Magillem solution (Connectivity, Registers, Packaging) automate everything from IP encapsulation and system assembly to register management

This combination allows XuanTie CPUs to fully realize their performance potential. Charlie elaborated on the quantifiable results of this collaboration in his speech:

“We have been working closely with the Xuantie team to validate Ncore interoperability across multiple RISC-V cores, ensuring consistency in both ACE protocol and the latest CHI protocol implementations. This collaboration has confirmed Ncore’s powerful system scalability, from heterogeneous multi-cluster designs to high-performance CHI configurations.

Working with cores such as the C908, C920, and R908, Ncore supports up to four clusters, achieving approximately 8.65 GB/s/GHz of system bandwidth and around 120 cycles of latency. On the C930 platform, Ncore scales to up to 16 cores, delivering approximately 30 GB/s/GHz of system bandwidth and around 110 cycles of latency.

These results fully demonstrate Ncore’s ability to deliver efficient, high-bandwidth, low-latency interconnect performance across a wide range of RISC-V systems.”

What does this mean? This pre-validated system IP combination, with Ncore at its core, enables RISC-V SoC design teams to achieve “out-of-the-box” usability with predictable performance and significantly reduced risk.

Ncore: The “Core Engine” for Cache Coherent Interconnect

So, what exactly is Ncore, the core of this collaboration?

 Ncore is a cache-coherent NoC IP built on years of production-proven silicon, supporting both Arm,RISC-V and others architectures. Its key advantages can be summarized in three keywords:

1. Scalable
   From small embedded systems to large designs with hundreds of billions of transistors and multiple chiplets, Ncore can handle it all. It supports cache-coherent expansion across up to four chiplets, with up to 4×128 GB/s bandwidth per link.
2. Configurable
   It simultaneously supports mainstream coherence protocols such as CHI-E, CHI-B, and ACE, allowing both new and legacy IP to coexist seamlessly. AXI non-coherent agents can also be integrated without difficulty.
3. Functional Safety
   Certified to ISO 26262 ASIL D, with automated FMEDA data generation, making functional safety design far less daunting.

What’s more, Ncore supports physical tiling in mesh topologies—like building with building blocks—allowing integration of up to 256 CPUs (in clusters of 8 cores), significantly reducing design, verification, and physical implementation time.

It is precisely these features that enable Ncore to act as the “central nervous system” in the XuanTie ecosystem, enabling high-bandwidth, low-latency cache-coherent interconnect for multi-core RISC-V systems.

From “Connection” to “Win-Win”

At the XuanTie Ecosystem Conference exhibition booth, many customers shared a common sentiment: previously, building a multi-core RISC-V chip meant spending months just solving cache coherence issues. Now, with Ncore at the heart of this complete system IP solution—complemented by Flex Family NoC IPs, CodaCache, and Magillem—teams can focus their efforts on their core business.

“Our goal is simple: reduce risk, connect IP, unify the system, ” Charlie summarized at the end of his speech.

And this encapsulates the essence of the Arteris and XuanTie partnership—making RISC-V’s journey toward high-performance faster and more reliable.

RISC-V is rapidly advancing into high-performance domains such as servers, AI accelerators, and automotive applications. While much of the industry focuses on clock speeds and raw compute power, it’s important to remember: how data moves is equally critical in determining a chip’s ultimate performance ceiling. And Ncore is the “hidden champion” working behind the scenes to ensure efficient data flow.

If you are planning your next-generation RISC-V SoC and aim to achieve both high performance and fast time-to-market, consider exploring Arteris’ system IP portfolio with Ncore at its core—a solution already validated within the XuanTie ecosystem.