How Synopsys and NVIDIA Are Accelerating Semiconductor Scaling in the AI Age
For decades, the task of creating masks for the manufacturing process has been an integral part of semiconductor manufacturing. As we move to more advanced nodes like 5nm, 3nm to 2nm, accelerating computational lithography turnaround time is instrumental in getting the chips fabricated efficiently in semiconductor manufacturing companies. Synopsys has been a pioneer in this area with advanced techniques to accelerate distributed processing in areas like supercomputers.
Our latest collaboration with NVIDIA to run Synopsys Proteus Optical Proximity Correction (OPC) software on the NVIDIA cuLitho software library is just one example of how we are providing another powerful way to accelerate that process on GPUs, taking it from weeks to days.
What this means for foundries and customers using these solutions is substantially faster turnaround times to develop chips on increasingly smaller process nodes. “As applications such as AI and machine learning drive the demand for greater density from smaller chips, lithography processes need a substantial speed boost to keep up with the pace of innovation,” said Vivek Singh, vice president, Advanced Technology Group, NVIDIA. “By collaborating with Synopsys, we are accelerating the massive computational workloads that currently consume tens of billions of CPU hours every year, enabling the creation of new lithography solutions and more predictability in future semiconductor technologies.”
Read on to learn more about why this collaboration is good news for semiconductor scaling—and every application demanding more performance from smaller footprints.
To read the full article, click here
Related Semiconductor IP
- PUF-based Post-Quantum Cryptography (PQC) Solution
- OPEN Alliance TC14 10BASE-T1S Topology Discovery IP
- HBM4 PHY IP
- 10-bit SAR ADC - XFAB XT018
- eFuse Controller IP
Related Blogs
- Analog Design and Layout Migration automation in the AI era
- Arm in the agentic era: Scaling the converged AI data center
- How Chip Makers Are Defying Complexity and Innovating Faster
- Ultra Ethernet Consortium Set to Enable Scaling of Networking Interconnects for AI and HPC