Traditional Cost Reduction Returns At 10nm, says Globalfoundries
Although there will not be the normal Moore’s Law 30% transistor cost reduction at 20nm, Globalfoundries reckons the successor node – 10nm – will see a return to the traditional cost curve
“The cost is going up but there are technology optimisations that can be implemented, ”
Subi Kengeri vice president for advanced technology architecture, told the Globalfoundries EMEA Technical Seminar in London on Monday.
At the 20nm node, Globalfoundries gets a 2x raw gate improvement and a 16% logic density benefit over 28nm giving cost savings of 7.5 to 8.5% over 28nm.
To read the full article, click here
Related Semiconductor IP
- SD/eMMC - GlobalFoundries 12LP, North/South Poly Orientation
- 802.11ah IP - GLOBALFOUNDRIES 22nm FDX
- MIPI C/D Combo PHY RX - GlobalFoundries 22FDX
- MIPI DPHY-TX - GlobalFoundries 22FDX process
- 512x8 Bits OTP (One-Time Programmable) IP, GLOBALFOUNDRIES 0.13um BCD 1.5V/5V Process
Related Blogs
- Is the Cost Reduction Associated with Scaling Over?
- How Much Cost Reduction Will 450mm Wafers Provide
- Want 10nm Wafers? That'll Cost You
- STMicroelectronics to give Globalfoundries a go
Latest Blogs
- FiRa 3.0 Use Cases: Expanding the Future of UWB Technology
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits