Traditional Cost Reduction Returns At 10nm, says Globalfoundries
October 10, 2013
Although there will not be the normal Moore’s Law 30% transistor cost reduction at 20nm, Globalfoundries reckons the successor node – 10nm – will see a return to the traditional cost curve
“The cost is going up but there are technology optimisations that can be implemented, ”
Subi Kengeri vice president for advanced technology architecture, told the Globalfoundries EMEA Technical Seminar in London on Monday.
At the 20nm node, Globalfoundries gets a 2x raw gate improvement and a 16% logic density benefit over 28nm giving cost savings of 7.5 to 8.5% over 28nm.
To read the full article, click here
Related Semiconductor IP
- All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX
- eFPGA on GlobalFoundries GF12LP
- ADPLL 2GHz Clock Generator - GLOBALFOUNDRIES 22FDX
- MIPI C/D Combo PHY RX - GlobalFoundries 22FDX
- 5 GHz 250 fs Jitter PLL - GlobalFoundries 22nm
Related Blogs
- Is the Cost Reduction Associated with Scaling Over?
- How Much Cost Reduction Will 450mm Wafers Provide
- Want 10nm Wafers? That'll Cost You
- UMC versus GLOBALFOUNDRIES
Latest Blogs
- Breaking the Silence: What Is SoundWire‑I3S and Why It Matters
- What It Will Take to Build a Resilient Automotive Compute Ecosystem
- The Blind Spot of Semiconductor IP Sales
- Scalable I/O Virtualization: A Deep Dive into PCIe’s Next Gen Virtualization
- UEC-LLR: The Future of Loss Recovery in Ethernet for AI and HPC