Addressing Heterogenous Verification and Validation Requirements for Compute Express Link (CXL) Designs Using Synopsys Protocol Continuum
August 18, 2021
Data is the new fuel powering critical use-cases for cloud /edge computing, and advances in AI. All aspects of data handling – gathering, storing, moving, processing, and dispersing – pose unique design implementation and verification challenges. The need for heterogenous computing has given exponential rise to application specific accelerators, pushing the industry to come up with a solution for efficient data handling and resource utilization. CXL is a processor interconnect protocol designed to support high bandwidth, low-latency interface from CPU to workload accelerators, maintaining memory coherency across heterogeneous devices, while addressing security needs of the user.
Related Semiconductor IP
- CXL 3.0 Premium Controller EP/RP/DM/SW 128-1024 bits with AMBA bridge and Advanced HPC Features (Arm CCA)
- CXL 3.0 Premium Controller EP/RP/DM 1024b/512b/256b/128b with AMBA bridge for CXL.io and LTI & MSI Interfaces
- CXL 3.0 Premium Controller EP/RP/DM 1024b/512b/256b/128b with AMBA bridge for CXL.io
- CXL 3.0 Premium Controller EP/RP/DM 1024b/512b/256b/128b
- CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge and Advanced HPC Features (Arm CCA)
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- Compute Express Link (CXL): All you need to know
- T&VS delivers Emulation and Validation services for Mobile SoC
- T&VS provides solution to Post Silicon Validation
- PCI Express: Delivering Needed Bandwidth for Open Compute Project
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