The CXL 3 Controller IP is designed to support dual-mode operation, allowing dynamic selection between host and device modes. It connects to standard 64GT/s PHYs through the PIPE 6.x interface and supports high data rates across various link widths.
CXL 3 Controller IP
Overview
Key Features
- Supports configuration of PCIe vs CXL protocol mode
- Supports both RC and EP modes
- Supports Link width support for x16, x8, x4, x2 and x1
- Supports memory cache for HDM-H, HDM-D, and HDM-DM modes
- Supports CXL Latency Optimized Mode
- Supports 32 GT/s and 64 GT/s precoding
- Supports Address Translation Service(ATS)
Benefits
- The CXL 3 Controller IP is forward compatible with CXL 3.x and backward compatible with previous versions, offering flexible configurations needed for advanced systems.
- It supports multiple channels and configurable CXL degraded modes, ensuring seamless integration with CXL devices and enabling high-performance data transfer.
- Ideal for versatile system designs, it accommodates all three CXL device types to facilitate efficient connectivity and scalable architecture.
Block Diagram
