Compliant with CXL Specification 2.0
CXL Controller
Overview
Key Features
- Compliant with CXL Specification version 2.0/1.1 and PCIe Base Specification 5.0 (32 Gbps per lane)
- Complaint with PIPE 5.x interface
- Supports X16, X8, X4, X2 and X1 lane widths
- Supports 512, 256 and 128 Data path widths
- Supports PCI Express Alternate Protocol
- Supports Dual Mode of operation (Host and Device)
- Supports CXL.io, CXL.cache, and CXL.mem protocols
- Supports Type1, Type 2 and Type 3 CXL device types
- Supports all requests and Response type packets for CXL.io, CXL.cache and CXL.mem protocols
- Independent packet oriented User Interface for each protocol (CXL.io, CXL.cache and CXL.mem protocols)
- Supports viral CXL containment feature
- Supports SR-IOV. ATS, FLR and AER for CXL.io
- Completely handles ordering rules for CXL.io, CXL.cache and CXL.mem in TX and RX directions
- Implements flow control logic in both directions
- Supports highly efficient flit-packing algorithm on TX path
- Supports Data poisoning
Technical Specifications
Short description
CXL Controller
Vendor
Vendor Name
SMIC
Silicon Proven:
14nm