Compute Express Link (CXL): All you need to know
November 10, 2021
In this blog post, we take an in-depth look at Compute Express Link ™ (CXL) 2.0, an open standard cache-coherent interconnect between processors and accelerators, smart NICs, and memory devices.
- We explore how CXL is helping data centers more efficiently handle the yottabytes of data generated by artificial intelligence (AI) and machine learning (ML) applications.
- We discuss how CXL technology maintains memory coherency between the CPU memory space and memory on attached devices to enable resource sharing (or pooling).
- We also detail how CXL builds upon the physical and electrical interfaces of PCI Express® (PCIe) 5.0 with protocols that establish coherency, simplify the software stack, and maintain compatibility with existing standards.
- Lastly, we review Rambus CXL solutions, which include the Rambus CXL 2.0 Interconnect Subsystem comprising a CXL 2.0 Controller and CXL 2.0 SerDes PHY. These solutions are now available with integrated Integrity and Data Encryption (IDE) modules which monitor and protect against cyber and physical attacks on CXL and PCIe links.
Let’s get started.
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Related Semiconductor IP
- CXL Verification IP
- CXL CONTROLLER IIP
- CXL Switch Verification IP
- CXL 3.0 Verification IP
- CXL Controller
Related Blogs
- PCIe 6.0 - All you need to know about PCI Express Gen6
- PCI Express 5 vs. 4: What's New? [Everything You Need to Know]
- Addressing Heterogenous Verification and Validation Requirements for Compute Express Link (CXL) Designs Using Synopsys Protocol Continuum
- PCIE 6.0 vs 5.0 - All you need to know