Complete Interface Solution for PCI Express 5.0 Launched
November 14, 2019
Rambus has announced a comprehensive interface solution for PCI Express (PCIe) 5.0 consisting of a new PCIe 5.0 PHY and a co-verified Northwest Logic Expresso 5.0 controller.
“Our high-speed SerDes and memory interface solutions make possible amazing advancements in performance-intensive applications in AI, data center, HPC, storage and networking,” said Hemant Dhulla, VP and GM of IP Cores. “Now we’ve added PCIe 5 to our industry-leading portfolio of high-speed interface solutions giving chip makers another tool to unleash the power of their designs.”
To read the full article, click here
Related Semiconductor IP
- Configurable PCI Express 4.0 Link Controller
- PCI Express PHY
- Multi-Channel Flex DMA IP Core for PCI Express
- PCIe - PCI Express Controller
- PCI Express PIPE PHY Transceiver
Related Blogs
- Complete Memory Interface Solution for HBM2E Launched
- Synopsys Delivers First Complete UFS 5.0 and M‑PHY v6.0 IP Solution for Next‑Gen Storage
- According with Cadence, PCI Express gen-3, to be the PCIe solution for the mainstream market as soon as in 2012
- Cadence support for the Open NAND Flash Interface (ONFI) 3.0 controller and PHY IP solution + PCIe Controller IP opening the door for NVM Express support
Latest Blogs
- Area, Pipelining, Integration: A Comparison of SHA-2 and SHA-3 for embedded Systems.
- Why Your Next Smartphone Needs Micro-Cooling
- Teaching AI Agents to Speak Hardware
- SOCAMM: Modernizing Data Center Memory with LPDDR6/5X
- Bridging the Gap: Why eFPGA Integration is a Managed Reality, Not a Schedule Risk