Complete Interface Solution for PCI Express 5.0 Launched
November 14, 2019
Rambus has announced a comprehensive interface solution for PCI Express (PCIe) 5.0 consisting of a new PCIe 5.0 PHY and a co-verified Northwest Logic Expresso 5.0 controller.
“Our high-speed SerDes and memory interface solutions make possible amazing advancements in performance-intensive applications in AI, data center, HPC, storage and networking,” said Hemant Dhulla, VP and GM of IP Cores. “Now we’ve added PCIe 5 to our industry-leading portfolio of high-speed interface solutions giving chip makers another tool to unleash the power of their designs.”
To read the full article, click here
Related Semiconductor IP
- PCI Express Verification IP
- PCI Express Synthesizable Transactor
- PCI Express to AMBA 4 AXI/3 AXI Bridge
- Multi-Port Switch IP for PCI Express
- IDE Security IP Modules for PCI Express 7.0
Related Blogs
- Complete Memory Interface Solution for HBM2E Launched
- According with Cadence, PCI Express gen-3, to be the PCIe solution for the mainstream market as soon as in 2012
- Cadence support for the Open NAND Flash Interface (ONFI) 3.0 controller and PHY IP solution + PCIe Controller IP opening the door for NVM Express support
- Interface Protocols, USB3, PCI Express, MIPI, SATA... the winners and losers in 2012