Why Focus Solely on CPU & GPU When Reducing SoC Power?
Interconnect clock gating cuts SoC energy consumption
The SoC interconnect is one area in which efforts to reduce power consumption need be re-evaluated.
Most efforts to control power consumption in System-on-Chip design are focused on the computational units, such as the CPU and GPU. However, other sections of the chip remain largely untapped for energy conservation measures. SoC designers may put themselves at a market disadvantage if they miss the opportunity to reap game-changing power savings from design measures that may cut overall power by as much as 10%.
The SoC interconnect is one area in which efforts to reduce power consumption need be re-evaluated. In computational units such as the GPU or CPU, clock-gating is one of several measures commonly applied to reduce power consumption, but in other areas of the chip, this may have been overlooked.
Related Blogs
- Arm enables the lowest power IoT devices with new Ambiq Apollo4 SoC on TSMC 22nm ULP and ULL libraries
- Why You Need to Consider Energy Efficiency of Your HPC SoC Early On
- Balancing GPU workloads on PowerVR hardware
- Designing Arm Cortex-M55 CPU on Arm Neoverse powered AWS Graviton2 Processors
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?