Why Focus Solely on CPU & GPU When Reducing SoC Power?
Interconnect clock gating cuts SoC energy consumption
The SoC interconnect is one area in which efforts to reduce power consumption need be re-evaluated.
Most efforts to control power consumption in System-on-Chip design are focused on the computational units, such as the CPU and GPU. However, other sections of the chip remain largely untapped for energy conservation measures. SoC designers may put themselves at a market disadvantage if they miss the opportunity to reap game-changing power savings from design measures that may cut overall power by as much as 10%.
The SoC interconnect is one area in which efforts to reduce power consumption need be re-evaluated. In computational units such as the GPU or CPU, clock-gating is one of several measures commonly applied to reduce power consumption, but in other areas of the chip, this may have been overlooked.
To read the full article, click here
Related Blogs
- Power, Not Area: Why Edge GPU Design Is Entering a New Era
- Why You Need to Consider Energy Efficiency of Your HPC SoC Early On
- Balancing GPU workloads on PowerVR hardware
- Scaling up vs scaling down. The real scoop on power-efficient GPUs for laptops
Latest Blogs
- IDS-Verify™: From Specification to Sign-Off – Automated CSR, Hardware Software Interface and CPU-Peripheral Interface Verification
- RISC-V and GPU Synergy in Practice: A Path Towards High-Performance SoCs from SpacemiT K3
- EDA AI Agents: Intelligent Automation in Semiconductor & PCB Design
- Why Security Can't Exist Without Trust
- Universal Browser Support for JPEG XL: Is Your Hardware Ready for the New Standard?