ARM ACE Assertion-Based Verification IP (ABVIP) Available Now
As anyone who has worked with ARM's AMBA 4 AXI Coherency Extensions -- a/k/a the "ACE" protocol -- knows, there are a ton of different configuration options and operational scenarios available to the designer. Of course, this flexibility and power presents a significant verification challenge. Hence, building on the success of our ACE Universal Verification Component (UVC) Verification IP product, we are excited to announce the immediate availability of the complementary Assertion-Based Verification IP (ABVIP) for ACE. Written in standard IEEE System Verilog Assertions (SVA), this new ACE ABVIP simultaneously supports simulation-centric ABV, pure formal analysis, and mixed formal and simulation verification flows.
In this 3 minute video, R&D Product Expert Joerg Muller outlines the main capabilities of this new product -- how it offers specific configuration, run time performance, and context-sensitive work-flow advantages in the SimVision debug environment vs. competitive offerings:
To read the full article, click here
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- Parameterizable compact BCH codec
- 1G BASE-T Ethernet Verification IP
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
Related Blogs
- Industry's First Verification IP for Arm AMBA CHI-G
- AMBA LTI Verification IP for Arm System MMU
- Synopsys Introduces the Industry's First Verification IP for Arm AMBA 5 CHI-F
- System Verification of Arm Neoverse V2-Based SoCs
Latest Blogs
- Physical AI at the Edge: A New Chapter in Device Intelligence
- Rivian’s autonomy breakthrough built with Arm: the compute foundation for the rise of physical AI
- AV1 Image File Format Specification Gets an Upgrade with AVIF v1.2.0
- Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES
- Integrating Post-Quantum Cryptography (PQC) on Arty-Z7