4nm 112G-ELR SerDes PHY IP
That's a lot of buzzwords! I assume you already know that SerDes stands for serializer-deserializer. It is an IP block that takes parallel data from buses on the chip and transforms it into a very high-frequency serial signal. In this case, the signal is 112 billion cycles per second, or 112G. The deserializer does the opposite, receiving a very fast signal on a single pin, and transforming it into parallel data on the chip. The transmission (serializer) side is the simpler of the two. The big complexity on the receive side is that there is no explicit clock, it has to be recreated from the data. Since there may be a lot of distortion on the channel (the electrical connection between the serializer on one chip and the deserializer on the other (or to the optical converter) aggressive equalization is required. If you actually see the signal before equalization, it seems amazing that this approach actually works.
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Related Blogs
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