4nm 112G-ELR SerDes PHY IP
That's a lot of buzzwords! I assume you already know that SerDes stands for serializer-deserializer. It is an IP block that takes parallel data from buses on the chip and transforms it into a very high-frequency serial signal. In this case, the signal is 112 billion cycles per second, or 112G. The deserializer does the opposite, receiving a very fast signal on a single pin, and transforming it into parallel data on the chip. The transmission (serializer) side is the simpler of the two. The big complexity on the receive side is that there is no explicit clock, it has to be recreated from the data. Since there may be a lot of distortion on the channel (the electrical connection between the serializer on one chip and the deserializer on the other (or to the optical converter) aggressive equalization is required. If you actually see the signal before equalization, it seems amazing that this approach actually works.
To read the full article, click here
Related Semiconductor IP
- Ultra-Low-Power Bandgap Voltage Reference in TSMC 4nm CMOS
- TSMC CLN4PLVT 4nm Ultra PLL - 15MHz-3000MHz
- TSMC CLN4P 4nm Ultra PLL - 15MHz-3000MHz
- TSMC CLN4PLVT 4nm Spread Spectrum PLL - 262MHz-1310MHz
- TSMC CLN4PLVT 4nm Spread Spectrum PLL - 524MHz-2620MHz
Related Blogs
- Cadence Demonstrates 112G-ELR SerDes IP on TSMC's 3nm Process Technology
- 16Gbps SerDes Multiprotocol Multilink PHY IP
- New 16Gbps Multi-link, Multi-protocol SerDes PHY Enhances Datacenter Connectivity
- Rambus showcases 56G Multi-Protocol SerDes (MPS) PHY at the Samsung Foundry Forum
Latest Blogs
- The Role of GPU in AI: Tech Impact & Imagination Technologies
- Time-of-Flight Decoding with Tensilica Vision DSPs - AI's Role in ToF Decoding
- Synopsys Expands Collaboration with Arm to Accelerate the Automotive Industry’s Transformation to Software-Defined Vehicles
- Deep Robotics and Arm Power the Future of Autonomous Mobility
- Explaining CAST’s Flexible IP Licensing