Cadence Demonstrates 112G-ELR SerDes IP on TSMC's 3nm Process Technology
The 3nm wave of technology is here! Cadence is proud to demonstrate its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s 3nm (N3E) process technology at the TSMC 2023 North America Technology Symposium this week. This is the latest addition to the Cadence 112G-ELR SerDes IP family. Riding the wave of More than Moore, FinFET transistors keep shrinking in TSMC’s 3nm process as they move towards system-in-package (SiP) designs. Combining the benefits of process technology advancement and Cadence’s best-in-class digital signal processor (DSP)-based SerDes architecture, the new 112G-ELR SerDes IP supports insertion loss (IL) of 45dB with exceptional power, performance, and area (PPA), making it ideal for hyperscale ASICs, artificial intelligence/machine learning (AI/ML) accelerators, switch fabric system-on-chips (SoCs) and 5G infrastructure applications.
To read the full article, click here
Related Semiconductor IP
Related Blogs
- 4nm 112G-ELR SerDes PHY IP
- Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
- IEDM: TSMC on 3nm Device Options
- Synopsys Accelerates Multi-Die System Designs With Successful UCIe PHY IP Tape-Out on TSMC N3E Process
Latest Blogs
- MIPS P8700 RISC-V Processor for Advanced Functional Safety Systems
- Boost SoC Flexibility: 4 Design Tips for Memory Subsystems with Combo DDR3/4 Interfaces
- High Bandwidth Memory Evolution from First Generation HBM to the Latest HBM4
- Keeping Pace with CXL Specification Revisions
- Silicon-proven LVTS for 2nm: a new era of accuracy and integration in thermal monitoring