Cadence Demonstrates 112G-ELR SerDes IP on TSMC's 3nm Process Technology
The 3nm wave of technology is here! Cadence is proud to demonstrate its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s 3nm (N3E) process technology at the TSMC 2023 North America Technology Symposium this week. This is the latest addition to the Cadence 112G-ELR SerDes IP family. Riding the wave of More than Moore, FinFET transistors keep shrinking in TSMC’s 3nm process as they move towards system-in-package (SiP) designs. Combining the benefits of process technology advancement and Cadence’s best-in-class digital signal processor (DSP)-based SerDes architecture, the new 112G-ELR SerDes IP supports insertion loss (IL) of 45dB with exceptional power, performance, and area (PPA), making it ideal for hyperscale ASICs, artificial intelligence/machine learning (AI/ML) accelerators, switch fabric system-on-chips (SoCs) and 5G infrastructure applications.
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