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LVDS IP

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Search (114)
Compare 114 LVDS IP from 16 vendors (1 - 10)
  • Library of LVDS IOs cells for TSMC 40LP
    • TSMC 40 LP
    • 2.5V/1.1V IO/Core transistors
    • Fully compliant with TIA/EIA-644-A-2001
    Block Diagram -- Library of LVDS IOs cells for TSMC 40LP
  • Library of LVDS IOs cells for TSMC 65LP
    • TSMC 65 LP
    • 2.5V/1.2V IO/Core transistors
    • Fully compliant with TIA/EIA-644-A-2001
    Block Diagram -- Library of LVDS IOs cells for TSMC 65LP
  • 1 Gbps Rail to Rail LVDS receiver
    • TSMC CMOS 0.065 um
    • 2.5 V analog power supply
    • 1.2 V digital power supply
    • 1.2 V CMOS input and output logic signals
    Block Diagram -- 1 Gbps Rail to Rail LVDS receiver
  • 2.4 Gbps LVDS transmitter
    • TSMC CMOS 0.065 um
    • 2.5 V analog power supply
    • 2.5 V CMOS input logic signals
    • 2.4 Gbps (DDR MODE) switching rates
    Block Diagram -- 2.4 Gbps LVDS transmitter
  • LVDS 160MHz 8-Lane PHY TX IP on TSMC 16FFC
    • The CL12491M8TIP160 transmitter converts parallel RGB data and 4bits of HYNC,VSYNC,DE and Control) of CMOS parallel data into serial LVDS data streams.
    • A phase-locked clock is transmitted in parallel with the data streams over a dedicated LVDS link.
    • The polarity of differential signals for each data lane can be controlled.
    Block Diagram -- LVDS 160MHz 8-Lane PHY TX IP on TSMC 16FFC
  • 1.2 Gbps LVDS transmitter/receiver
    • TSMC CMOS 180 nm
    • 3.3 V power supply
    • 1.2 Gbps (DDR MODE) switching rates (600 MHz)
    • Half-duplex or full-duplex operation mode
    Block Diagram -- 1.2 Gbps LVDS transmitter/receiver
  • Rail to rail LVDS receiver 1 Gbps
    • iHP SiGe BiCMOS 0.13 um
    • 3.3 V power supply
    • 1 Gbps (DDR MODE) switching rates
    • Conforms to TIA/EIA-644 LVDS standards without hysteresis
    Block Diagram -- Rail to rail LVDS receiver 1 Gbps
  • 1 Gbps LVDS Transmitter
    • iHP SiGe BiCMOS 0.13 um
    • 3.3 V power supply
    • 1 Gbps (DDR MODE) switching rates
    • Conforms to TIA/EIA-644 LVDS standards
    • Optimized for pad-limited layout design
    Block Diagram -- 1 Gbps LVDS Transmitter
  • Programmable CMOS LVDS Transmitter/Receiver
    • TSMC 0.13 um CMOS
    • 3.3 V analog power supply
    • 1.2 V digital power supply
    • 1.2V CMOS input and output logic signals
    • 8-step (3-bit) adjustable transmitter output current (range from 0.75 mA to 6.5 mA)
    Block Diagram -- Programmable CMOS LVDS Transmitter/Receiver
  • LVDS interfaces
    • Wide operating range
    • High data rates
    • Very flexible programmability
    • Excellent signal integrity
    • TIA/EIA644A LVDS and sub-LVDS compatibility
    • Receiver also compatible with LVPECL
    Block Diagram -- LVDS interfaces
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