Library of LVDS IOs cells for TSMC 65LP

Overview

The nSIO2000_TS65LP_2V5_1V2 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/1.2V or 1.8V/1.2V, designed on the TSMC 65 LP technology. The library is composed according to the customer’s choice of cells.

Key Features

  • Standard-compliant to TIA/EIA-644-A-2001
  • Built-in, low parasitic ESD protection
  • Easily integrates with TSMC I/O library cells
  • All-in-ring® topology, so no core silicon area is used by LVDS
  • The same cells operate with 2.5V/1.2V or 1.8V/1.2V power supplies
  • Standby/power down mode
  • Digital loopback functions to ease ATE testing
  • Up to 2 Gbps data rate LVDS

Block Diagram

Library of LVDS IOs cells for TSMC 65LP Block Diagram

Applications

  • Multi-purpose reconfigurable IO
  • Point-to-point, point-to-multipoint or bus-based IC high-speed data communications
  • Intra-package (e.g. MCM or SIP) inter-die high-speed data communications
  • Backplane high-speed data communications
  • High-speed serial communications (HDMI, SATA, PCIeX, etc.)
  • Communication to LCD/OLED screens
  • Video sensor digital data interface

Deliverables

  • GDS II layouts
  • LEF abstracts
  • CDL netlists
  • Liberty timings
  • Verilog description
  • A full datasheet
  • An integration note

Technical Specifications

Foundry, Node
TSMC 65 LP
Maturity
Silicon proven
TSMC
Silicon Proven: 65nm LP
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Semiconductor IP