KA16UGLVDS01ST001 is a LVDS IO handling data rate up to 50Mbps with a maximum loading of 60pF. The differential voltage swing can be programmable from 0.35V to 1V. The output enable control function can be activated to decide the IO as input/output function. This IP also includes the IO PAD.
LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
Overview
Key Features
- Process: Silterra 0.16um CMOS 1P5M Process
- Supply Voltage Range: AVDD33 = 3.3v +/-10%, AVDD18 = 1.8v +/-10%
- Ambient Temperature: 0°C~80°C
- Compatible with BLVDS_25 of Spartan-3A FPGA
- Bi-direction (half-duplex)
- External Termination Resistor: RT = 120Ω
- Maximum Running Data Rate 50 Mbps with Maximum Loading 60pF
- <3-bit> Programmable Output Differential Voltage from 0.35V to 1V
- ESD: 2kV HBM and 200V MM
Benefits
- The differential voltage swing can be programmable from 0.35V to 1V.
Block Diagram
Applications
- Consumer
- Industrial Electronic
Deliverables
- Compatible with BLVDS_25 of Spartan-3A FPGA
Technical Specifications
Short description
LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
Vendor
Vendor Name
Foundry, Node
Silterra 0.16um CMOS 1P5M Process
Maturity
Silicon Proven
Availability
NOW
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