IP Catalog > Memory & Libraries IP > I/O Library IP > High-speed IP > LVDS IP > HDMI, LVDS, RF and Analog Pads Library in 45nm / 40nm

HDMI, LVDS, RF and Analog Pads Library in 45nm / 40nm

Overview

A 1.0V to 5V Analog IO Library that includes an HDMI, LVDS, and Analog/RF Low Capacitance pad set in 45nm/40nm HPM processes.

This library is a collection of analog-only IO and Power/Ground pads, including ESD. The target applications are high-performance analog interfaces, including HDMI, RF, LVDS, basic analog, and other applications. The pads include several specialty features: fail-safe, low capacitance, high ESD protection, and IEC robustness. The IOs are designed to trigger and protect interfaces during Electrical Overstress (EOS) events during normal operation. A key feature of the library is the extremely small footprint of the inline IO set, only 2.2um bigger than the bond pad itself. Capacitance can range from <150fF to 250fF and is scalable based on the customers’ needs between ESD robustness and capacitive loading.

Key Features

  • In-line Low Cap Analog: 50um pitch x 60um height (HDMI, LVDS, RF, Analog, and Low-Cap IOs)
  • Dual-row, staggered pitch of 25um x 150um height (Analog, RF, LVDS, and Low-Cap IOs)
  • AVDD = 1.0V to 3.3V nominal, 5V tolerant HDMI option
  • Capacitance 150fF to 250fF including bond pads*
  • HBM >4000V*
  • CDM >800V*
  • MM >300V*
  • IEC >2kV option*
  • EOS protection
  • Junction temperature range: -40?C to 125?C
  • Can integrate with TSMC standard IO
  • HDMI AND LVDS PAD FEATURES
    • Includes Power and GND pads
    • <250fF per IO including Bondpad
    • 1.8V to 3.3V power supply (HDMI)
    • 1.8V Power Supply (LVDS and analog)
    • 5V Tolerant (HDMI only)
    • Fail-Safe IO (HDMI only
    • Pad Macros provide for ideal parasitic matching between differential signal pins

Deliverables

  • MODELS AND SUPPORT FILES
    • GDS layouts
    • LEF Abstracts
    • CDL netlist for simulation and LVS
    • Functional models in behavioral Verilog with timing arcs
  • FRONT-END DEVICES
    • 2.5V overdriven 3.3V thick-oxide NMOS and PMOS; No ESD implant layer or special masks required
    • Back-end: Metal1 to Metal8, AP Bondpad layer for Wirebond, using Circuit-Under-Pad construction

Technical Specifications

Foundry, Node
TSMC 45nm/40nm
Maturity
Silicon-Proven
Availability
Immediate
TSMC
In Production: 130nm G , 130nm LP
Silicon Proven: 40nm G , 45nm LP
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