Vendor: Certus Semiconductor Category: Analog

HDMI, LVDS, RF and Analog Pads in TSMC 45/40nm

A 1.0V to 5V Analog I/O library that includes an HDMI, LVDS, and Analog/RF Low Capacitance pad set in TSMC 45/40nm HPM process.

Contact Provider Request Datasheet
TSMC 40nm G View all specifications

Overview

A 1.0V to 5V Analog I/O library that includes an HDMI, LVDS, and Analog/RF Low Capacitance pad set in TSMC 45/40nm HPM process.

This library is collection of analog only IO and Power/Ground pads that include ESD. The target applications are high performance analog interfaces including HDMI, RF, LVDS, basic analog and other applications. The pads include a host of specialty features including fail safe, low capacitance, high ESD protection, and IEC robustness. The IOs are designed to trigger and protect interfaces during Electrical Overstress (EOS) events during normal operation. A key feature of the library is the extremely small footpr int of the inline IO set, only 2.2um bigger than the bond pad itself. Capacitance can range from <150fF to 250fF and is scalable based on the customers needs between ESD robustness and capacitive loading.

Key features

  •  In-line low-cap analog, 50um pitch x 60um height
  •  Dual-row, staggered pitch of 25um 150um height
  •  AVDD = 1.V to 3.3V nominal, 5V tolerant HDMI option
  •  Capacitance 150fF to 250fF including bond pads*
  •  HBM >4kV*, CDM >800V*, IEC >2kV option*
  •  EOS Protection
  •  Junction temperature range: -40C to 125C
  •  Can integrate with TSMC standard I/O
  •   HDMI and LVDS PAD Features 
    •  Includes Power and Ground pads 
    •  <250fF per I/O including bondpad 
    •  1.8V to 3.3V power supply (HDMI) 
    •  5V Tolerant (HDMI only)
    •  Fail-Safe I/O (HDMI only)
    •  Pad Macros provide ideal parasitic matching between differential signal pads

Block Diagram

DG40 block diagram

What’s Included?

  • Models and Support Files
    • GDS Layouts
    • LEF Abstracts
    • CDL netlist for simulation and LVS
    • Functional models in behavioral Verilog with timing arcs
  • Front-end Devices
    • 2.5V overdriven 3.3V thick-oxide NMOS and PMOS; No ESD implant layer or special masks required.
    • Back-end: Metal 1 to Metal 8, AP bondpad layer for Wire-bond, using Circuit-Under-Pad construction.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 40nm G —

Specifications

Identity

Part Number
DG40
Vendor
Certus Semiconductor
Type
Silicon IP

Provider

Certus Semiconductor
HQ: United States
Certus Semiconductor has assembled several of the world’s foremost experts in IO and ESD design to offer our clients the ability to affordably tailor their IO libraries into the optimal fit for their products. Certus is offering the semiconductor industry a unique approach to custom IO libraries, including tailored IO designs, and ESD solutions based on simulations leveraging specialized silicon ESD models. In addition to offering fast turnaround custom IO designs, Certus offers independent ESD design, review and debug services. Through partnerships, Certus is also able to provide ESD testing & TLP support.
Contact Certus Semiconductor

Learn more about Analog IP core

Real PPA improvements from analog IC migration

Analog migration projects live or die on numerous metrics – it is not easy, to say the least. Three very critical metrics are PPA, Performance, Power and Area. Here’s what most analog designers already know: when you’re porting IP to a new process, the real goal isn’t improvement—it’s preservation.

Analog Foundation Models

In this work, the authors introduce a general and scalable method to robustly adapt LLMs for execution on noisy, low-precision analog hardware.

AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing

Analog/mixed-signal circuits are key for interfacing electronics with the physical world. Their design, however, remains a largely handcrafted process, resulting in long and error-prone design cycles. While the recent rise of AI-based reinforcement learning and generative AI has created new techniques to automate this task, the need for many time-consuming simulations is a critical bottleneck hindering the overall efficiency. Furthermore, the lack of explainability of the resulting design solutions hampers widespread adoption of the tools.

Why Anti-tamper Sensors Matter: Agile Analog and Rambus Deliver Comprehensive Security Solution

If your device processes valuable data, controls a critical function, or connects to a wider network, it’s a target. Attackers don’t just try to break software; they increasingly physically tamper with hardware; probing, fault injecting, or opening enclosures to bypass protections and extract secrets. The consequences range from IP theft and fraud to orchestrated downtime across fleets of connected devices.

Frequently asked questions about Analog I/O Pad Library IP cores

What is HDMI, LVDS, RF and Analog Pads in TSMC 45/40nm?

HDMI, LVDS, RF and Analog Pads in TSMC 45/40nm is a Analog IP core from Certus Semiconductor listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Analog?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Analog IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP