Dual-Port SRAM IP
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Dual-Port SRAM IP
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146
Dual-Port SRAM IP
from 14 vendors
(1
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10)
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MRAM Synthesizable Transactor
- Supports all the MRAM commands as per the MR2A16A and MR0A08B specifications.
- Supports Symmetrical high-speed read and write with fast access time.
- Supports SRAM Compatible timing
- Supports native non-volatility
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Memory Compiler
- 70-90% power reduction
- Unmatched performance
- Multi-technology support
- Tailored for design needs
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CodaCache® Last Level Cache IP
- Standalone IP
- 1.2 GHz frequency in 16FF+TT process
- Protocol interoperability: AMBA AXI 4
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GF 0.13um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
- Automatic Power Down
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CSMC 0.18um 90% shrunk Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
- Automatic Power Down
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CSMC 0.13umLP Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
- Low Leakage
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
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CSMC 0.13um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via1 ROM Compiler
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
- Automatic Power Down
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Memory Compiler
- High-Density Memory Compilers
- Ultra-High-Speed Memory Compilers
- Low-Power Memory Compilers
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Dolphin SPI Controller
- Dolphin SPI Controller supports:
- + Master only operation
- + Slave only operation
- + Master and slave operation
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Foundation IP (Memory Compliers & Standard Cell Libraries)
- Memory Compilers
- Standard Cell Libraries