Embedded Memories IP for TSMC
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Embedded Memories IP
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High Speed Single Port Compiler on TSMC 40nm ULP
- Low voltage
- Ultra low power data retention
- Self biasing
- Soft error immunity
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Embedded flash IP, 1.8V/5V TSMC 180nmBCD
- Supports high temperature and long retention life time for severe automotive requirement
- Low power in Program/Erase operation for power critical applications
- Requires few (2~3) additional masks
- No change to SPICE model of Standard CMOS process, for re-using existing design and IP
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eTCAM (Embedded Ternary Content Addressable Memory IP
- One cycle operation latency (without priority encoder)
- Valid Bit per entry to reduce power
- Valid Bit reset in one cycle support
- Mask input option for bit-write and masked search key
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eTCAM (Embedded Ternary Content Addressable Memory IP
- One cycle operation latency (without priority encoder)
- Valid Bit per entry to reduce power
- Valid Bit reset in one cycle support
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sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
- Foundry sponsored - sROMet compiler - TSMC 55 nm uLPeFlash - Non volatile memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
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sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M
- REDUCE DIE COST
- Via 1 programmable ROM
- Key patent for high density with a single programming layer
- Gain in density over alternative ROM designs
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Memory Compilers
- Dolphin provides a wide range of Memory Compilers and Specialty Memory (ROM, Multi Port RF, CAM, etc.) optimized to meet even the most demanding requirements for high performance, high density and low power.
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Memory Compiler in TSMC (16nm,22nm,28nm,40nm,55nm,90BCD+,110nm,152nm,180BCD)
- Synchronous read/write operation
- Low leakage current and lower operation power consumption
- Minimum metal layer requirement: 4/3 metal layers
- High density layout structure and small area design
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TSMC CLN16FFC Ultra High Density One Port Register File
- The Ultra High Density One Port Register File operates within voltage range from 0.72 V to 0.88 V and junction temperature range from -40 °C to 125 °C. The available supported macro size is configurable from 128 bits to 72K bits. The Compiler is divided into 3 groups according to their column selection numbers (Mux=1, 2 or 4).
- Pins and metal layers
- 1P4M (2Xa1Xd_h): 4 metal layers used and top metal is MXd.
- Power mesh supported with M4 pins
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Embedded Flash IP,64Kx8 bits for 1.8V/5V/32V HV
- Logic Embedded IP
- Programming with channel hot electron injection, erasing with FN erase
- High yield performance
- Small IP size