eTCAM (Embedded Ternary Content Addressable Memory IP

Overview

Key Features

• One cycle operation latency (without priority encoder)
• Valid Bit per entry to reduce power
• Valid Bit reset in one cycle support
• Mask input option for bit-write and masked search key
• Additional power emulation library support
• BIST support with redundancy

Benefits

• Small area:
  • By optimizing the peripheral circuit of memory, particularly small area is realized.
• Low power:
  • Optimized low leakage design, valid bit control and search mask will make low power performance achievable. What s more, providing a design environment that allows customer to confirm the power saving feature according to the actual usage conditions.
• IDM-oriented design quality:
  • Many product proven.

Block Diagram

Deliverables

• User s guide
• Data sheet
• Hard macro FE library ( Verilog model, LEF, Liberty, Fastscan, dftmax, Tetramax )
• Hard macro BE library ( CDL, GDS )
• Soft macro ( RTL BIST Wrapper )

Technical Specifications