Capturing a UART Design in MyHDL & Testing It in an FPGA
André Castelan Prado, Editor, Embarcados
EETimes (9/9/2014 06:05 PM EDT)
The universal asynchronous receiver/transmitter (UART) is an old friend to embedded systems engineers. It's probably the first communications protocol that we learn in college. In this article, we will design our very own UART using MyHDL.
MyHDL is a free, open-source Python library developed by Jan Decaluwe. Its goal is to be a powerful hardware description language. The idea is to apply the new concepts that have appeared in the software industry to hardware design, such as test-driven development, functional tests, and high-level abstraction. The system also generates synthesizable VHDL and Verilog code from the MyHDL design. The idea is to verify everything in Python and then press the "Go" button to generate a VHDL or Verilog representation that can be synthesized and loaded into an FPGA.
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