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UART IP

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Search (169)
Compare 169 IP from 55 vendors (1 - 10)
  • UART - Ensures reliable serial communication and protocol compliance in SoCs
    • The UART Verification IP provides a comprehensive solution for validating UART communication interfaces in System-on-Chip (SoC) designs. It simulates both transmission and reception functionality to ensure data integrity. This IP supports error injection, debugging tools, and protocol compliance checking. It is ideal for ensuring reliability and protocol compliance in UART-based peripherals used in various applications, from simple devices to advanced systems.
    Block Diagram -- UART - Ensures reliable serial communication and protocol compliance in SoCs
  • Simulation VIP for UART
    • Mode
    • Synchronous, Asynchronous
    • Transmission Mode
    • Full-Duplex, Half-Duplex
    Block Diagram -- Simulation VIP for UART
  • UART Verification IP
    • Fully compatible with 16550.
    • Transmit and receive commands allow the user to transmit and receive UART data.
    • Support additional functionality of IRDA, RS232, RS422, RS485 and GPIO.
    • Configurable baud rate.
    Block Diagram -- UART Verification IP
  • MIPI DEBUG UART Verification IP
    • APB common support
    • Supports different transfer types including IDLE, WRITE and READ.
    • Supports unaligned address accesses.
    • Slave memory map support.
    Block Diagram -- MIPI DEBUG UART Verification IP
  • UART Synthesizable Transactor
    • Fully compatible with 16550
    • Supports transmit and receive commands allow the user to transmit and receive UART data
    • Supports additional functionality of IRDA, RS232, RS422, RS485 and GPIO
    • Supports full duplex operation
    Block Diagram -- UART Synthesizable Transactor
  • UART CONTROLLER IIP
    • Implemented in Unencrypted Verilog, VHDL and SystemC
    • Compliant with Standard UART 16550 Specification
    • Full UART Functionality
    • Transmit and receive commands allow the user to transmit and receive UART data
    Block Diagram -- UART CONTROLLER IIP
  • UART Assertion IP
    • Specification Compliance
    • Fully compatible with 16550.
    • Transmit and receive commands allow the user to transmit and receive UART data.
    • Support additional functionality of IRDA, RS232, RS422, RS485 and GPIO.
    Block Diagram -- UART Assertion IP
  • DO-254 UART
    • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
    • Configurable baud rate, number of data bits, parity and stop bits.
    • Fully deterministic handshake interface that allows easy handling of reception/transmission requests
    • Single clock domain fully synchronous design
    Block Diagram -- DO-254 UART
  • A bridge to convert the slave SPI interface to the master UART interface and vice versa
    • Programmable data length UART (8 bits)
    • Programmable 1, 2 bit Stop
    • Programmable Data Direction (LSB first or MSB first)
    • Programmable Clock polarity and phase (CPOL and CPHA) – 4 mode
  • APB UART 16550
    • This is a complete implementation of a 16550 UART.
    • The UART contains the following main sections: Configuration Registers, Baud Rate, Generator, Transmitter, Receiver, Interrupt Generation Logic, Modem Control Logic
    Block Diagram -- APB UART 16550
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Semiconductor IP