UART IP

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Compare 152 IP from 50 vendors (1 - 10)
  • UART Serial Interface Controller
    • UART-compatible interface
    • AMBA AXI4-Lite bus
    • Full duplex
    • Custom baud rate generation
    Block Diagram -- UART Serial Interface Controller
  • UART Serial Interface Controller
    • UART-compatible interface
    • AMBA APB3 bus
    • Full duplex
    • Custom baud rate generation
    Block Diagram -- UART Serial Interface Controller
  • UART to I2C Bridge Controller
    • UART compliant with only 2-wires required (Tx/Rx)
    • UART baud rates from 9600 to 921600
    • I2C bus support for 100 kbps, 400 kbps or custom rates
    Block Diagram -- UART to I2C Bridge Controller
  • Single Channel UART with Scalable Rx-FIFO
    • Single channel UART
    • Flexible baudrate generator
    • Status and error registers
    • Scalable RxFIFO (2/4/8/16 bytes deep)
    Block Diagram -- Single Channel UART with Scalable Rx-FIFO
  • UART Serial Interface Controller
    • UART compliant
    • Simple command interface
    • Baud rates from 9600 to 921600
    • Custom baud rates also supported
    Block Diagram -- UART Serial Interface Controller
  • DO-254 UART
    • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
    • Configurable baud rate, number of data bits, parity and stop bits.
    • Fully deterministic handshake interface that allows easy handling of reception/transmission requests
    • Single clock domain fully synchronous design
    Block Diagram -- DO-254 UART
  • APB UART 16550
    • 16450/16550 Compatible
    • 16 byte transmit FIFO
    • 16 byte receive FIFO
    • Modem control
    Block Diagram -- APB UART 16550
  • APB UART with optional ISO7816-3
    • 7 or 8 data bits.
    • 1 or 2 stop bits.
    • Parity bit (None / Even / Odd / Mark / Space).
    • Optional RTS/CTS flow control.
    Block Diagram -- APB UART with optional ISO7816-3
  • Tiny UART
    • Majority Voting Logic
    • Adds or deletes standard asynchronous communication bits (start, stop, parity) to or from the serial data.
    • In UART mode receiver and transmitter are double buffered to eliminate the need for precise synchronization between the CPU and serial data.
    • Independently controlled transmit, receive, line status, and data set interrupts.
    Block Diagram -- Tiny UART
  • SDIO to UART Controller
    • Compliant with SD Physical Specification Version 2.00 and SDIO Specification Version 2.00.
    • Supports SPI, 1-bit and 4bit SD modes.
    • Supports SDIO Interrupt feature
    • Supports all mandatory SDIO Commands/Response types
    Block Diagram -- SDIO to UART Controller
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Semiconductor IP