Save power in IoT SoCs by leveraging ADC characteristics
Manuel Mota, Synopsys
EDN (August 21, 2015)
Power-sensitive applications such as Internet-of-Things (IoT) require a comprehensive power savings strategy within the system-on-chip (SoC). Techniques relying solely on the use of traditional power down modes and low supply voltage may not be enough to achieve the required power targets. The analog block is often assumed to be too sensitive and not compatible with aggressive power management techniques.
However, a good understanding of the analog block’s characteristics can enable low-power SoC designs. In this article we take a closer look at the analog-to-digital converter (ADC) IP interfacing with external sensors in a general purpose IoT SoC design and describe its relevant characteristics that can be leveraged at the system level to achieve low-power consumption.
Challenges of traditional low-power techniques
IoT applications, possibly operating on coin cell batteries or energy harvesting, are driving the requirements for very low-power consumption SoC designs across the industry. In order to sustain operation for a long period of time without replacing the batteries, designers must make the most of the available power reduction techniques.
The traditional approach relies on reduction of the SoC’s supply voltages and on the finer geometry process’ smaller feature size to reduce active power. This approach increases system costs and potentially, leads to higher leakage power.
At the system level, it is possible to implement low-power techniques by identifying blocks in the chip that can be powered down when certain actions are being performed. It is also possible to adjust the clock rate and supply level to the minimum that sustains the performance of the required actions, thus saving additional power.
An IoT SoC’s typical activity profile is characterized by its very short duty cycle: most of the circuit is often in idle mode; only a small portion of the circuit is intended to be always active in order to scan the environment and activate the remaining circuitry when needed. (Figure 1). The always active circuitry is placed on a dedicated power island and uses high Vth devices or even thick oxide devices to minimize leakage power. The remaining circuitry can be switched off from the power supply to limit its leakage.
To read the full article, click here
Related Semiconductor IP
- ADC
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 10-bit Pipeline ADC - Tower 180 nm
- 12-bit/16-bit SAR ADC
- 106dB, 24-bit audio three-channels ADC in TSMC 40uLP
Related Articles
- Think Big for Ultra-Low Power IoT SoCs
- How NoCs ace power management and functional safety in SoCs
- ReGate: Enabling Power Gating in Neural Processing Units
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
Latest Articles
- Analog Foundation Models
- Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators
- RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI
- Exclude Smart in Functional Coverage
- A 0.32 mm² 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection