Think Big for Ultra-Low Power IoT SoCs
Kurt Shuler, VP Marketing, Arteris
EETimes (8/4/2016 09:42 AM EDT)
Some of the best ideas in creating breakthrough IoT innovation could be gleaned from the design of much larger SoCs.
The so-called Internet of Things is rife with design challenges.
Many SoC engineers in this field are trying to cram the greatest possible processing power within the lowest possible power budget.
That’s what it’s going to take to provide value at the network edge as more and more devices deploy sensors, microcontrollers and modems to send information back to the core for big data analytics. Or so the conventional wisdom goes.
But that could be a mistake.
To read the full article, click here
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
Related Articles
- Save power in IoT SoCs by leveraging ADC characteristics
- Novel and efficient power grid design for lesser metal layer process SOC's
- Define Analog Sensor Interfaces In IoT SoCs
- Reducing chip IR drop in backward-compatible power bar-limited LQFP SoCs
Latest Articles
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
- A 129FPS Full HD Real-Time Accelerator for 3D Gaussian Splatting
- SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation
- TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks