FastPath: A Hybrid Approach for Efficient Hardware Security Verification
By Lucas Deutschmann 1, Andres Meza 2, Dominik Stoffel 1, Wolfgang Kunz 1 and Ryan Kastner 2
1 RPTU Kaiserslautern-Landau, Germany
2 UC San Diego, USA
Abstract
Many verification methods have been proposed to detect microarchitectural information leakage in response to the surge of security breaches in hardware designs. These sophisticated efforts have gone a long way toward preventing attackers from breaking the system’s confidentiality. However, each approach has its own set of weaknesses: it may not be scalable enough, exhaustive enough, flexible enough to meet changing requirements or fit well into existing verification flows.
We propose FastPath, a hybrid verification methodology that combines the efficiency of simulation with the exhaustive nature of formal verification. FastPath employs a structural analysis framework to automate the method further. Our experimental results compare FastPath to a state of-the-art formal approach, showing a significant reduction in manual effort while achieving the same level of exhaustive confidence. We also discovered and contributed a fix for a previously unknown leak of internal operands in cv32e40s, a RISC-V processor intended for security applications.
Index Terms — Hardware Security, Information Flow Tracking, Simu lation, Formal Verification, Data-Oblivious Computing.
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- AVSBus v1.4.1 Verification IP
- Flipchip 1.8V/3.3V I/O Library with ESD-hardened GPIOs in TSMC 12nm FFC/FFC+
- DDR5 MRDIMM PHY and Controller
- APV - Advanced Professional Video Codec
Related White Papers
- A formal-based approach for efficient RISC-V processor verification
- Interstellar: Fully Partitioned and Efficient Security Monitoring Hardware Near a Processor Core for Protecting Systems against Attacks on Privileged Software
- A closer look at security verification for RISC-V processors
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
Latest White Papers
- FastPath: A Hybrid Approach for Efficient Hardware Security Verification
- Automotive IP-Cores: Evolution and Future Perspectives
- TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models