Planning reset strategy: Flow & functionality in OVC
Parag Goel, Pushkar Naik, Applied Micro Circuits Corp.
3/9/2011 8:01 AM EST
Overview
Reset strategy, which has long been a part and parcel of the design methodology, playing a vital role in the successful working of any given design, has become increasingly important on the verification methodology front. Reset forms a fundamental property of any protocol/system and is the first step in the sequence of operations done for any system bring up. The following write-up addresses this essential strategy to be followed during verification using an OVM-based test bench.
While developing an OVM–based IP (i.e. OVM Verification Component (OVC)), it is required to get a clear perspective on the way it behaves and recovers from reset application during the course of simulation.
To read the full article, click here
Related Semiconductor IP
- USB 20Gbps Device Controller
- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
- AGILEX 7 R-Tile Gen5 NVMe Host IP
- 100G PAM4 Serdes PHY - 14nm
- Bluetooth Low Energy Subsystem IP
Related White Papers
- SoC tool flow techniques for detecting reset domain crossing problems
- An Automated Flow for Reset Connectivity Checks in Complex SoCs having Multiple Power Domains
- Optimizing Floorplan for STA and Timing improvement in VLSI Design Flow
- RISC-V in 2025: Progress, Challenges,and What’s Next for Automotive & OpenHardware
Latest White Papers
- aTENNuate: Optimized Real-time Speech Enhancement with Deep SSMs on RawAudio
- Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference
- Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems
- CRADLE: Conversational RTL Design Space Exploration with LLM-based Multi-Agent Systems
- On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures