SoC tool flow techniques for detecting reset domain crossing problems
Arjun Pal Chowdhury, Neha Agarwal, and Ankush Sethi, Freescale India
embedded.com (August 13, 2014)
In a sequential system on chip designs, if the reset of source register is different from the reset of destination register, even though the data path is in same clock domain, this can cause an asynchronous crossing path to occur which can cause metastability at destination register [1].
This paper proposes a verification tool flow which can be used with any SoC structural verification tool to detect such reset domain crossing (RDC) problems. It also describes some techniques to make the SoC design tools you use intelligent enough to weed out false violations.
To read the full article, click here
Related Semiconductor IP
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
- UCIe RX Interface
- Very Low Latency BCH Codec
- 5G-NTN Modem IP for Satellite User Terminals
- 400G UDP/IP Hardware Protocol Stack
Related Articles
- Dealing with SoC metastability problems due to Reset Domain Crossing
- Understanding Clock Domain Crossing Issues
- Clock Domain Crossing Glitch Detection Using Formal Verification
- The Challenge of the Clock Domain Crossing verification in DO-254
Latest Articles
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS
- A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA
- VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration
- PDF: PUF-based DNN Fingerprinting for Knowledge Distillation Traceability