Leveraging RISC-V as a Unified Heterogeneous Hardware & Software Platform for Next-Gen AI Chips
By Akeana
Today’s SoC developers need flexibility in computing systems and interconnect schemes that allow them to meet compute/watt requirements and the needs of CPU-xPU AI systems.
In this webinar, learn how Akeana is enabling SoC developers to use RISC-V-based solutions for next-generation AI chips. Our solutions include IP for RISC-V processors, accelerators, data movement engines, and compute subsystem interconnects. By the end of this video, attendees will have knowledge about:
- AI CPU compute array, scaling up performance for new AI algorithms
- AI xPU compute solutions with Akeana’s broad range of In-Order control/wide vector processors, data movement engines
- Flexible connection, performance operation of Akeana multi-core, GEMM engine, partners accelerators and customers hardware blocks
Related Semiconductor IP
- MIPI I3C Master RISC-V based subsystem
- ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
- RISC-V CPU IP
- RISC-V Vector Extension
- RISC-V Real-time Processor
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