Demonstration of the Akeana 5100 core with Hypervisor
This video shows the Akeana 5100 core enabled with Hypervisor running Linux OS various applications, on a Synopsys HAPS-100 emulation platform
Related Semiconductor IP
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Compact Embedded RISC-V Processor
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
Related Videos
- The Evolution of HBM
- Managing the Massive Data Throughput: AI-Based Designs and The Value of NoC Tiling
- Analog AI Chips for Energy-Efficient Machine Learning: The Future of AI Hardware?
- Ask the Experts: The State of AI
Latest Videos
- Powering the AI Supercycle: Design for AI and AI for Design - Anirudh Devgan
- Scaling AI from Edge to Data Center with SiFive RISC-V Vectors
- Paving the Road to Datacenter-Scale RISC-V
- Enhancing Data Center Architectures with PCIe® Retimers, Redrivers and Switches
- How UCIe 3.0 Redefining Chiplet Architecture: From Protocol to Platform