Paving the Road to Datacenter-Scale RISC-V
By Martin Dixon, Engineering Director, Google
The computing industry has shifted to an era of specialization, and Google’s heterogeneous datacenters—powered by x86, Arm, GPUs, and TPUs—are at the forefront of this trend. This keynote delivers our playbook for this new reality.
We will share insights from our legacy single architecture to our multi-architecture journey, detailing how AI was used to automate the complex porting of our software stack from x86 to other ISAs like Arm and RISC-V. We will discuss how we can build on this "paved road" of tooling and expertise to further accelerate our joint RISC-V journey. We conclude with a call to action, to move faster, together, to build on our model with collaborators like the RISE Project to accelerate the pace of innovation and adoption for RISC-V.
Related Semiconductor IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Compact Embedded RISC-V Processor
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
Related Videos
- Hardware Innovation in the World's First RISC-V 50 TOPS AI Compute for Mass Production Development
- The Next Computing Megatrends are Enabled by RISC-V
- The Rise of RISC-V
- Bringing High-Performance RISC-V Platforms to Life
Latest Videos
- Paving the Road to Datacenter-Scale RISC-V
- Enhancing Data Center Architectures with PCIe® Retimers, Redrivers and Switches
- How UCIe 3.0 Redefining Chiplet Architecture: From Protocol to Platform
- Teradyne Testimonial: Silicon Creations' 16nm SerDes Enables Fastest TTM and Most Cost-Effective Teradyne ASIC Development To-Date
- Webinar: Unpacking System Performance – Supercharge Your Systems with Lossless Compression IPs