Scaling AI from Edge to Data Center with SiFive RISC-V Vectors
AI with Sally
In this podcast, John Simpson, senior principal architect for SiFive’s Intelligence products, talks about how RISC-V processors are designed to support AI workloads from the edge to the data center.
Related Semiconductor IP
- Multi-core capable 32-bit RISC-V CPU with vector extensions
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 8-stage dual issue, in-order, superscalar processor with dual vector processing units (1024-bit VLEN/512-bit DLEN)
- Multi-core capable RISC-V processor with vector extensions
- RISC-V Debug & Trace IP
Related Videos
- Arm: Scaling AI Compute from Edge to Cloud
- BrainChip Expands IP Business Model with AKD1500 Production to Accelerate Edge AI Deployment
- Enhancing Data Center Architectures with PCIe® Retimers, Redrivers and Switches
- Hardware Innovation in the World's First RISC-V 50 TOPS AI Compute for Mass Production Development
Latest Videos
- Scaling AI from Edge to Data Center with SiFive RISC-V Vectors
- Paving the Road to Datacenter-Scale RISC-V
- Enhancing Data Center Architectures with PCIe® Retimers, Redrivers and Switches
- How UCIe 3.0 Redefining Chiplet Architecture: From Protocol to Platform
- Teradyne Testimonial: Silicon Creations' 16nm SerDes Enables Fastest TTM and Most Cost-Effective Teradyne ASIC Development To-Date