UMC denies 65-nm yield issues
Foundry blames tight capacity for 'isolated' customer supply requirements
Dylan McGrath, EE Times
(07/07/2009 12:37 PM EDT)
SAN FRANCISCO -- United Microelectronics Corp. (UMC) Tuesday (July 7) denied a report that it experienced yield problems on its 65-nm process and said some isolated problems in meeting customer requirements were the result of tight capacity due to customer rush orders.
On Monday (July 6) Taiwan IT media outlet DigiTimes cited unidentified industry sources in reporting that programmable logic vendor Xilinx Inc. experienced supply constraints due to problems with UMC's 65-nm yield. Xilinx (San Jose, Calif.) last week lowered its June quarter revenue estimate, citing a shortfall in sales due to inability to meet strong demand for its Virtex-5 FPGAs.
Dylan McGrath, EE Times
(07/07/2009 12:37 PM EDT)
SAN FRANCISCO -- United Microelectronics Corp. (UMC) Tuesday (July 7) denied a report that it experienced yield problems on its 65-nm process and said some isolated problems in meeting customer requirements were the result of tight capacity due to customer rush orders.
On Monday (July 6) Taiwan IT media outlet DigiTimes cited unidentified industry sources in reporting that programmable logic vendor Xilinx Inc. experienced supply constraints due to problems with UMC's 65-nm yield. Xilinx (San Jose, Calif.) last week lowered its June quarter revenue estimate, citing a shortfall in sales due to inability to meet strong demand for its Virtex-5 FPGAs.
To read the full article, click here
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
Related News
- Foundries have 28-nm yield issues, say execs
- Yield And Reliability Issues With Integrating IP
- Date 2002 conference to spotlight IP, SoC issues
- Genesys Testware Adds Support for Fuse Arrays to Improve the Yield of Embedded Memories
Latest News
- M31 Collaborates with TSMC to Achieve Tapeout of eUSB2V2 on N2P Process, Advancing Design IP Ecosystem
- Menta’s eFPGA Technology Adopted by AIST for Cryptography and Hardware Security Programs
- Silicon Creations Celebrates 20 Years of Global Growth and Leadership in 2nm IP Solutions
- TSMC Debuts A13 Technology at 2026 North America Technology Symposium
- Cadence Collaborates with TSMC to Accelerate Design of Next-Generation AI Silicon