TVS announces new CPU Verification tool development
February 23, 2015 -- TVS is pleased to announce the development of a new “Event Stream Generator”.
Processors (CPU, GPU, DSP, etc.) are becoming more complex and require more verification. The current best practise in processor verification is instruction stream generation.
The TVS instruction stream generator (asureISG) will have the following major features
- Offline generation: the instructions are generated in advance of simulation for quicker generation speeds.
- Sequence generation: sequences of instructions can push a design into the corners where the bugs lurk!
- Multicore support: asureISG can be programmed to generation instructions for multiple cores allowing it to generate sequences of instruction streams for multiple cores. Those sequences can interlaced with defined synchronisation points for multicore verification.
- Coverage support: coverage models can be built into the generation to help direct the generation.
asureISG is currently under development with TVS key clients but we are open to more early adopter partners who want to influence the development.
Related Semiconductor IP
- DVB-S2X Wideband LDPC/ BCH Encoder
- Audio Sample Rate Converter
- 1-56Gbps Serdes - 7nm (Multi-reference Clock)
- 1-56Gbps Serdes - 7nm (Ultra Low Latency)
- 1-56Gbps Serdes - 7nm (Area-optimized)
Related News
- Imperas and Metrics Collaborate to Jump Start RISC-V Core Design Verification Using Open Source Instruction Stream Generator
- eInfochips announces SPI4.2 and CCIR656 Stream Generator Design IP
- Mentor Catapult HLS Enables Stream TV's R&D Group SeeCubic to Develop Glasses-Free 3D Digital Display IP
- SystemC-based UVM testing from TVS streamlines IP for Blu Wireless Technology
Latest News
- Neumonda and Ferroelectric Memory Company Collaborate in the Commercialization of Non-Volatile DRAM
- MLE Releases Network Protocol Accelerator Platform (NPAP) Version 2.5.0
- A 10-cent RISC-V microcontroller from China? Why not?
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Cyient Spin-off Eyes Global ASIC Market