TSMC's Chip Scaling Efforts Reach Crossroads at 2nm

By Alan Patterson, EETimes (June 7, 2021)

Perpetuating Moore’s Law — the observation that the transistor density in a typical chip doubles every two years — poses a number of challenges at the 3nm node, yet Taiwan Semiconductor Manufacturing Corp. (TSMC) remains optimistic.

There are many predictions Moore’s Law is likely to hit a wall soon, but “how soon?” is open to debate. Also, there are technologies that promise ongoing increases in performance that are not dependent on doubling transistor density. The timing of all that will have far-reaching implications. At last week’s TSMC 2021 Technology Symposium, TSMC CEO C. C. Wei gave the example of data centers, which consume over one percent of global electricity generated.

“Estimates suggest global electricity usage from data centers is projected to grow from five to forty times between 2010 to 2030. Why do projections vary so widely?” Wei asked. “Divergent estimates are partly due to the difficulty of making an accurate projection of our footprint. There are too many variables to consider, including whether Moore’s Law can continue.”

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