CXL Adds Port Bundling to Quench AI Thirst
By Gary Hilson, EETimes | December 4, 2025
The evolution of the CXL protocol is being driven by the ever-increasing demands of AI—the latest update includes new features that satisfy memory-hungry GPUs.
CXL 4.0, released by the CXL Consortium, doubles bandwidth from 64GT/s to 128GT/s with no added latency to enable rapid data movement between CXL devices. In a briefing with EE Times, Anil Godbole, the consortium’s marketing working group chair, said the evolution of the specification reflects the move toward more memory intensive applications, heterogenous computing and disaggregation of memory from compute.
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