Intel, TSMC to detail 2nm processes at IEDM
By Peter Clarke, eeNews Europe (October 8, 2024)
Intel’s attempts to get back to the leading-edge in chipmaking and foundry TSMC’s steps defining that leading-edge will be on show at this year’s International Electron Devices Meeting (IEDM) coming up in December, in San Francisco.
In a late news paper, researchers from TSMC will unveil the N2 manufacturing process, which is a nominal 2nm process designed for computing in AI, mobile and high-performance computing. In the following paper in the same session Intel engineers will provide details of scaling RibbonFETs, the name Intel gives to its nanosheet transistors.
To read the full article, click here
Related Semiconductor IP
- Network-on-Chip (NoC)
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- UCIe PHY (Die-to-Die) IP
- UCIe-S 64GT/s PHY IP
- UA Link DL IP core
Related News
- Analog Bits to Demonstrate IP Portfolio on TSMC 3nm and 2nm Processes at TSMC 2025 Technology Symposium
- Alphawave Semi Tapes Out Breakthrough 36G UCIe™ IP on TSMC 2nm, Unlocking Foundational AI Platform IP on Nanosheet Processes
- Intel and Cadence Expand Partnership to Enable Best-in-Class SoC Design on Intel's Advanced Processes
- Siemens qualifies industry-leading IC design solutions for Intel Foundry processes
Latest News
- GUC Monthly Sales Report – November 2025
- Global Semiconductor Sales Increase 4.7% Month-to-Month in October
- CXL Adds Port Bundling to Quench AI Thirst
- Tenstorrent and AutoCore Announce Strategic Partnership to Power High-Performance RISC-V Automotive Computing with AutoCore.OS
- Tenstorrent Announces Availability of TT-Ascalon™