Leakage divided by more than 250 at 180 nm eLL with Dolphin Integration Panoply of memory and standard cells
Meylan, France – August 26, 2011. As electronic intelligence is pervading battery-powered consumer and industrial devices, their Systems On Chip must come up with more complex features - while limiting the impact on power consumption and die cost.
Such power sensitive applications must rely on architectures of Silicon IPs which enable:
- The best combination of logic density and power consumption
- Islets with diverse low power modes: multi voltage, retention, extinction
- Capability for efficient operation at ultra low voltage
Dolphin Integration is the unique provider to address all of such challenges at the architectural level with the launch of a complete Panoply of Memories and Standard Cells for the new 180 nm eLL process at TSMC.
Dolphin Integration's Panoply is a comprehensive set of silicon IPs for low power and Dual Voltage
- Single Port RAM generator
- Standard Cell library of the celebrated Reduced Cell Stem flavor
- Metal programmable ROM generator
- Efficient Power Regulators
Benchmark results of Dolphin SpRAM versus Standard SpRAM at 180 nm

- 5% denser
- Twice less leaky in G process, 250 times less leaky in eLL process!
- 3 times less dynamic power in G and eLL process!
- Support for low voltage down to 1.2 V for additional power savings
For building ultra low power islets at 180 nm eLL
- Low voltage operation enabled down to 1.2 V
- Low Power cells for power gating and state retention of logic blocks
- Embedded power switches for partial or complete shut down of memory blocks
- UPF/CPF compatibility
For right-on-first-pass silicon
- TSMC 9000 qualification
- Design methodology ensuring functionality at low voltage
Ask for more information on product performances and key features, please click here
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation and foundry parnerships. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, resilient to noise and drastic for low power-consumption, together with engineering assistance and product evolutions customized to their needs.
For more information about Dolphin, visit: www.dolphin.fr/sesame
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- Dolphin Integration announces a new stem of Standard Cells for extremely low leakage in TSMC 90LP
- Standard Cells reducing leakage 40 to 60 times at 90 and 65 nm from Dolphin Integration
- JEDEC Updates Standard for Low Power Memory Devices: LPDDR5
- JEDEC Publishes Update to LPDDR5 Standard for Low Power Memory Devices
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack