Standard Cells reducing leakage 40 to 60 times at 90 and 65 nm from Dolphin Integration
Meylan, France – March 03, 2011. The SESAME BIV (Battery Interface Voltage) library of Standard Cells with its Flip-Flop patented for Low Voltage operation, is the winners' choice to in-house libraries for low-power applications.
SESAME BIV can be applied for two different and complementary purposes:
- Direct Battery supply: using the SESAME BIV for synthesizing small logic blocks directly connected to the battery with no need for an intermediate regulator.
- Low Leakage islet: SESAME BIV is superior for synthesizing an always-on logic block - such as Real Time Clocks - by maintaining the leakage to a level lower than HVt-based libraries.
Highlights
Direct battery supply
- Functional from 1.1 V up to 3.6 V thanks to patented flip flops
- Simple implementation: islets directly powered by the external battery
- No need for dedicated regulator
Low Leakage features
- Leakage reduction of 40 to 60 times in typical process
- Possibility to remove regulators and their leakage
Consistent kit for a straightforward design-in
- Isolation cells
- Ultra Low Leakage Level Shifters
- Custom PVT support
Optimal Design for Yield
- Design methodology ensuring High-Yield circuits despite Mismatch
- Specification of OCV margins
Already celebrated at 180 nm and 130 nm SESAME BIV is being released for 90 nm and 65 nm designs.
Have a quick look at:
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own EDA solutions enabling Integration Hardware Modeling (IHM) and Application Hardware Modeling (AHM) as well as early Power and Noise assessment, plus engineering assistance for Risk Control. For more information about Dolphin, visit: www.dolphin.fr/sesame
Related Semiconductor IP
- RISC-V CPU IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
Related News
- Dolphin Integration offers first standard cell library to enable a leakage reduction of 1/350 at 65 and 55 nm
- Leakage takes priority at 65 nm
- Dolphin Integration announces a new stem of Standard Cells for extremely low leakage in TSMC 90LP
- DOLPHIN Integration releases a ROM in 65 nm with Ultra high density and ultra low leakage
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers