TSMC Details Silicon Road Map
FinFETs will fly from 16nm to 7nm
Rick Merritt, EETimes
3/16/2016 06:30 AM EDT
SAN JOSE, Calif.—Taiwan Semiconductor Manufacturing Co. Ltd. is ramping its 16nm process and making progress on plans to roll out 10 and 7nm nodes over the next two years. The news injected optimism in a crowd of about 1,500 attendees at a Silicon Valley event here where the world’s largest independent chip foundry shared its long-sought success with FinFETs and the great unknown beyond.
Some observers were underwhelmed, claiming TSMC’s road map to 7nm will only bring it in line with the 14nm process in which Intel is currently ramping its Skylake CPUs.
Indeed, even TSMC executives noted its 10 and 7nm nodes will have minimum feature sizes of about 20 and 14nm, respectively. And they all use the same fundamental FinFET transistor structures Intel pioneered at 22nm and 14nm. However, they also reported significant progress on research on post-FinFET devices.
To read the full article, click here
Related Semiconductor IP
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- TSMC CLN5FF GUCIe LP Die-to-Die PHY
- Flipchip 1.8V/3.3V I/O Library with ESD-hardened GPIOs in TSMC 12nm FFC/FFC+
- TSMC CLN3FFP HBM4 PHY
- Wi-Fi 7(be) RF Transceiver IP in TSMC 22nm
Related News
- SIA road map defines performance-SoC challenges
- TSMC Adds High-K Metal Gate Low Power Process to 28nm Road Map
- Nvidia's road map drives graphics, ARM into enterprise
- ARM Gives Peek at Road Map
Latest News
- GUC Monthly Sales Report – August 2025
- eSOL and Infineon Enter Strategic Partnership for Next-generation Automotive Platforms Based on RISC-V/TriCore/Arm Microcontrollers
- Synopsys and GlobalFoundries Establish Pilot Program to Bring Chip Design and Manufacturing to University Classrooms
- Cadence to Acquire Hexagon’s Design & Engineering Business, Accelerating Expansion in Physical AI and System Design and Analysis
- IntoPIX Receives 2025 Emmy® Award For The Development Of JPEG XS