TSMC Reports Foundry's First 32-Nanometer Technology with Functional SRAM
â Taiwan Semiconductor Manufacturing Company (TSE: 2330, NYSE: TSM) today announced it has developed the first 32-nanometer (nm) technology that supports both analog and digital functionality. The company made its announcement through a paper presented at todayâs IEEE International Electron Devices Meeting in Washington, DC. The paper also revealed that the company had proven the full functionality of the 2Mb SRAM test chip with the smallest bit-cell at the 32nm node.
This leading edge technology is optimized for low power, high density and manufacturing margins with optimal process complexity. Low power technology integrated with high density SRAM, low standby transistors, analog and RF functions, and copper and low-k interconnects is ideal for system on chip (SoC) devices targeted in mobile applications. TSMC plans to provide complete digital, analog and RF functions, and high density memory capabilities at 32nm node.
Noteworthy in the announcement is the fact that this is the first 32nm low-power technology that did not have to resort to high-k gate dielectric and metal gates to achieve its performance characteristics. In addition, a 0.15um² high density SRAM cell has been realized by 193nm immersion lithography using double patterning approach.
âWith this announcement, TSMC continues to lead the industry by pushing the boundaries of advanced technology,â said Dr. Jack Sun, vice president R&D, TSMC. âThe achievement made at 32nm technology node is yet another testimony to our long-term investment and commitment in advanced technology development to help our customers bring their leading-edge products first to market.â
About TSMC
TSMC is the worldâs largest dedicated semiconductor foundry, providing the industryâs leading process technology and the foundry industryâs largest portfolio of process-proven libraries, IP, design tools and reference flows. The Companyâs total managed capacity in 2006 exceeded seven million (8-inch equivalent) wafers, including capacity from two advanced 12-inch GigaFabs, four eight-inch fabs, one six-inch fab, as well as TSMCâs wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com
Related Semiconductor IP
- Simulation VIP for Ethernet UEC
- CAN-FD Controller
- Bluetooth® Low Energy 6.2 PHY IP with Channel Sounding
- Simulation VIP for UALink
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
Related News
- Analog Bits to Demonstrate IP Portfolio on TSMC 3nm and 2nm Processes at TSMC 2025 Technology Symposium
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- M31 Collaborates with TSMC to Advance 2nm eUSB2 IP Innovation
- Sofics Delivers Remarkable PPA & R Performance Near Physical Limits on TSMC 2nm Technology
Latest News
- WAVE-N v2: Chips&Media’s Custom NPU Retains 16-bit FP for Superior Efficiency at High TOPS
- Quintauris releases RT-Europa, the first RISC-V Real-Time Platform for Automotive
- PQShield's PQCryptoLib-Core v1.0.2 Achieves CAVP Certification for a broad set of classical and post-quantum algorithms
- M31 Debuts at ICCAD 2025, Empowering the Next Generation of AI Chips with High-Performance, Low-Power IP
- Perceptia Begins Port of pPLL03 to Samsung 14nm Process Technology