Sofics Delivers Remarkable PPA & R Performance Near Physical Limits on TSMC 2nm Technology

Sofics’ solutions empower IC design with great Power-Performance-Area and Robustness improvements

GISTEL, BELGIUM – June 25, 2025 – Sofics bv, a world leading solution provider specializing in physical layout and design, with a focus on the built-in robustness of integrated circuits that demand superior power, performance, and area (PPA), today announced the silicon validation of its IP for TSMC’s cutting-edge 2nm technology, which adopts nanosheet transistor structure. This marks a significant milestone in the long-standing partnership between Sofics and TSMC, and underscores Sofics’ continued commitment to shorter times-to-market and unique value for leading applications in the world’s most advanced semiconductor process nodes.

As a key and long-standing partner of TSMC’s Open Innovation Platform® (OIP) ecosystem and a member of TSMC OIP Design Center Alliance (DCA) and IP Alliance since 2010, Sofics has collaborated with TSMC from an early stage to validate its IP on TSMC’s 2nm process. Through continued layout and design innovation, higher PPA and robust performance was achieved in on-chip ESD devices and interface circuits.

Key results include:

• Validated robustness for interfaces running at 0.75V, 0.9V, 1.2V, 1.5V, or 1.8V.
• Low parasitic capacitance ESD for high speed, high bandwidth, and high frequency applications
• Great area savings on GPIO cells over existing industry targets
• GPIO circuits operating at 1.2 or 1.8V to enable communication with legacy chips

“ Our early 2nm IP deployment underscores the strength of our over 15-year collaboration with TSMC.

More than 90 customers have already adopted our IP solutions across various TSMC process technologies.

With this latest milestone, we are ready to support next-gen SoCs and chiplets with unparalleled power-performance-area and robustness.”

Koen Verhaege, Sofics CEO

These capabilities are tailored for advanced system-on-chip (SoC) and chiplet designs in AI, HPC, smartphone, and data-center applications. Sofics engaged with more than ten leading semiconductor companies to define these needs, ensuring early alignment with market expectations. The GPIO area is reduced up-to half their defined targets, and with a relentless focus on leakage reduction, very significant power gains are achieved too.

“ Our collaboration with TSMC OIP ecosystem partners like Sofics on our most advanced technologies is critical for enabling our joint customers to create next-generation designs for AI and HPC innovations.

We will continue to work closely with our OIP partners to deliver competitive advantages in performance and power-efficiency for our customers”

Lluis Paris, senior director of ecosystem and alliance management division, TSMC North America

Sofics’ collaboration with TSMC in early silicon validation ensures fabless designers can access pre-verified, high-performance IP that accelerates time-to-market, reduces risk, and cuts costs — especially vital for ultra-low power and chiplet-based architectures.

The IP is now available for immediate licensing to customers utilizing TSMC 2nm nanosheet technology.

About Sofics

Sofics (www.sofics.com) is a leading independent provider of semiconductor IP for on-chip ESD, I/O and reliability solutions. Sofics IP is integrated in more than 5000 tape outs across CMOS, FinFET, BCD and SOI processes – and is now ready for nanosheet.