SPI-S From the OIF Is Ready for Business
New Scalable Protocol Can Handle Hundreds of Gigabits Per Second
FREMONT, Calif. -- December 18, 2006 -- The Optical Internetworking Forum (OIF) has finalized the highly anticipated Scalable System Packet Interface (SPI-S) implementation agreement, making the high speed interface available for immediate deployment. SPI-S is a robust, channelized, streaming-packet interface that scales from 6 Gb/s to hundreds of Gb/s for chip-to-chip and backplane applications. A successor to the widely deployed OIF SPI 4.2 interface, SPI-S leverages the OIF’s Common Electrical Interface (CEI) to take advantage of high rate serial physical interconnects.
“The OIF’s existing System Packet Interface SPI 4.2 is the most widely deployed chip-to-chip streaming interconnect for high speed data paths,” said Dave Stauffer, of IBM and chair for the OIF’s Physical and Link Layer Working Group. “Given the highly scalable nature of the new SPI-S, it should have legs to stand for a decade or more as the industry’s next definitive streaming-packet interface. The speed and number of bit lanes employed by SPI-S can be directly scaled to very high rates.”
SPI-S is specified to run over CEI, which is defined at 6 and 11 Gb/s for both short reach and long reach applications. SPI-S can also be used with other physical interconnects including OIF’s SxI-5. The OIF also recently announced the initiation of a CEI-25 project to extend the CEI serial interface into the 25 Gb/s range. The scalable nature of SPI-S will allow it to take advantage of CEI-25 when the next generation interconnect is fully defined.
SPI-S uses either industry-standard 64B66B framing or optionally, the enhanced OIF CEI Protocol (CEI-P) framing that provides Forward Error Correction (FEC) support, yet retains a 64/66 clock ratio. FEC is likely to be useful when 11 Gb/s PHYs are used in backplane applications and when future, higher speed PHYs are employed.
SPI-S also retains the high-availability focus of the SPI family of interfaces. Like those other protocols, SPI-S is defined to be self-recovering from a catastrophic event on its interface such as a protective switchover of a card.
The SPI-S implementation agreement is available to the public at www.oiforum.com/public/documents/OIF-SPI-S-01.0.pdf
About the OIF
Launched in April of 1998, the OIF is the only industry group uniting representatives from data and optical networking disciplines, including many of the world's leading carriers, component manufacturers and system vendors. The OIF promotes the development and deployment of interoperable networking solutions and services through the creation of Implementation Agreements (IAs) for optical, interconnect, network processing and component technologies, and optical networking systems. The OIF actively supports and extends the work of national and international standards bodies with the goal of promoting worldwide compatibility of optical internetworking products. Working relationships or formal liaisons have been established with the IEEE 802.3, IETF, ITU-T Study Group 13, ITU-T Study Group 15, IPv6 Forum, MFA Forum, MEF, MVA, ATIS OPTXS, ATIS TMOC, Rapid I/O, TMF, UXPi and the XFP MSA Group. More information on the OIF can be found at www.oiforum.com http://www.oiforum.com.
Related Semiconductor IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
- Neuromorphic Processor IP
- Lossless & Lossy Frame Compression IP
Related News
- LEDA Systems ® and Modelware ® Announce Partnership for Silicon Proven SPI 4 Phase 2 Semiconductor IP providing 10 Gb/s Transport Solutions for Communications Systems-on-a-Chip.
- TriCN'S SPI-4.2 I/O Interface Technology Supports NPFSI, SFI and SPI Standards
- Vitesse and Xilinx Demonstrate OIF Interoperability Enabling 10Gbps Ethernet at OFC 2003
- Silicon Logic Engineering SPI 4 Phase 2 is Silicon Proven
Latest News
- GUC Monthly Sales Report – August 2025
- eSOL and Infineon Enter Strategic Partnership for Next-generation Automotive Platforms Based on RISC-V/TriCore/Arm Microcontrollers
- Synopsys and GlobalFoundries Establish Pilot Program to Bring Chip Design and Manufacturing to University Classrooms
- Cadence to Acquire Hexagon’s Design & Engineering Business, Accelerating Expansion in Physical AI and System Design and Analysis
- IntoPIX Receives 2025 Emmy® Award For The Development Of JPEG XS