TriCN'S SPI-4.2 I/O Interface Technology Supports NPFSI, SFI and SPI Standards

TriCN's approach to SPI-4.2 acts as a fully digital SerDes

San Francisco, CA - July 8, 2002 -- TriCN, a leading developer of intellectual property (IP) for high-speed I/O interface technology, today announced its SPI-4.2 Dynamic Alignment technology can be deployed to support three different OC-192 interface standards: Network Processing Forum Streaming Interface (NPFSI), SONET Framer Interface (SFI-4.1), and Common Switch Interface (CSIX). TriCN currently has customers for the product, which is available in TSMC's 0.18um and 0.13um process.

"Our goal in developing our SPI-4.2 Dynamic Alignment solution was to produce IP that was modular enough to offer a range of specific interface applicability, while also delivering the very highest throughput performance available in the market," said Ron Nikel, CEO and Chief Technology Officer of TriCN. "Interface specific design is the essence of TriCN's product approach. Our SPI-4.2 solution exactly fits the needs of chip producers implementing a high-speed NPFSI, SFI or the SPI interface."

TriCN's SPI-4.2 SerDes

TriCN's System Packet Interface (SPI-4.2) is a fully digital SerDes solution that consists of a transmitter hard macro (TriDL-SPI4-T), a receiver hard macro (TriDL-SPI4-DR) and SPI-4 low-voltage differential signaling (LVDS) I/O's. These interface macros and input/output (I/O) solutions provide up to 1.5 Gb/s per pin and 24Gb/s aggregate data rates, to meet even the most aggressive throughput requirements.

Because TriCN's SPI-4.2 Dynamic Alignment solution is a fully digital implementation, designers can potentially realize up to a 20% savings in silicon area, over a comparable analog implementation, and as much as a 50% savings in power over comparable analog solutions. This I/O solution employ's TriCN's unique (patent-pending) approach to skew compensation, for maximum skew tolerance and maximum throughput levels, providing bit-level de-skewing capable of handling skew levels up to +/- 1UI at 1.5Gb/s per pin.

TriCN's modular approach to the SPI-4.2 interface allows customized SPI-4.2 solutions to be implemented seamlessly. This modular approach, combined with a core-side interface bus that can be programmed to be 32, 64, or 128 bits wide, allows for straightforward integration of TriCN's SPI-4 Phase 2 solution. TriCN's SPI-4.2 I/Os can support both standard Bondwire BGA or Flipchip packaging.

About TriCN

Founded in 1997, San Francisco, California-based TriCN is the creator of a new class of intellectual property (IP) known as Interface-Specific I/O. This IP is designed for IC developers addressing strategic, bandwidth-intensive communications, networking, storage and memory applications whose data throughput performance is currently stymied by I/O bottlenecks. TriCN's patent-pending technology overcomes these I/O bottlenecks by delivering validated, industry-leading I/O performance and bandwidth density while dramatically streamlining design complexity and time-to-market. TriCN's customers range from startup to established fabless semiconductor and systems companies, including Philips, MIPS Technologies, SGI, IBM, Cognigine, Internet Machines, and Apple Computer.

For more information, please visit TriCN's web site at www.tricn.com .
 

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