Silicon Logic Engineering SPI 4 Phase 2 is Silicon Proven

SLE is Platinum Status in IBM IP Collaboration Program

EAU CLAIRE, Wis., Feb 16, 2004-- Silicon Logic Engineering (SLE), a provider of high-end digital application specific integrated circuit (ASIC) and system-on-chip (SOC) intellectual property (IP) and design services, today announced that its System Packet Interface (SPI)-4 Phase 2 is silicon proven and available in 7 different technologies.

SLE's SPI-4.2 for high-end networking applications has reached Platinum status in IBM's IP Collaboration Program. This means SLE's SPI-4 Phase 2 has been designed in and is in production with at least one IBM ASIC customer. SLE and IBM's customer, Astute Networks, used IBM's leading edge CU-11 0.13-micron process technology and SLE's SPI-4 Phase 2 for the production of Astute Network's Intelligent Protocol Processor.

Keith Klarer, Vice President of Engineering for Astute Networks, commented: "SLE offered us quality IP, provided excellent design services to compliment the IP, and was a great company to work with. The design worked with first-pass-success." Astute Network's Intelligent Protocol Processor leads the field in stateful protocol processors, providing a high performance scaleable architecture for intelligent SAN switches, storage arrays, iSCSI and FCIP gateways, and blade servers. The protocol processor implements storage and network protocols such as TCP/IP, FCIP, iSCSI, and Fibre Channel; and performs mirroring, snapshot, failover, and real time traffic monitoring.

The IP is now available in 7 different technologies as a soft macro for companies that need customization and is available in two technologies as a hard macro, for companies that need faster integration. The 7 different technologies include:

  • Agilent, 0.13um
  • IBM CU-11, 0.18um
  • IBM SA-27e, 0.18um
  • ST Microelectronics HCMOS9, 0.13um
  • TI SR-40, 0.13um
  • TSMC (Artisan), 0.13um
  • Virtual Silicon, 0.13 um

"High-end systems developers are demanding best-in-class third party chip IP that is silicon proven in leading semiconductor processes," said Jeff West, president of SLE. "Our company has a long history of designing ASICs and we are very pleased to be able to offer silicon proven IP as well as another design success story."

SLE's SPI-4 Phase 2 is a complete solution that includes both the physical and link layers, and incorporates a proprietary real-time tuning algorithm. It is a fully digital, standard cell based implementation that requires no PLLs or DLLs. SLE's SPI-4 Phase 2 is ideal for packet and cell transfer in key applications such as OC-192, Packet over Sonet/SDH, and 10 Gigabit Ethernet. Developed by the Optical Internetworking Forum (OIF), the SPI-4 Phase 2 standard is fast emerging as one of the most important integration standards in the history of telecommunications and data networking.

About Astute Networks

Astute Networks is a leading designer of intelligent silicon-based protocol acceleration technologies. The company markets essential intelligent networking technologies to OEM partners worldwide that allow them to deliver competitive advantages and cost-effective solutions to IT professionals. Formed in April 2000 and based in San Diego, Calif., Astute Networks has raised more than $23 million in venture capital funding led by U.S. Venture Partners (USVP) and BA Venture Partners. Additional information on Astute is available at www.astutenetworks.com

About SLE

SLE specializes in right-first-time, leading edge, digital ASIC and system design services that address all aspects of complex ASIC development from concept to silicon. SLE's proven and repeatable Think Physical design process, tools, and semiconductor intellectual property reduce time-to-market and are provided by one of the most experienced VLSI design teams in the industry. Founded in 1996 by former Cray Research engineers, SLE is headquartered in Eau Claire, Wisconsin. For more information, visit us at www.siliconlogic.com.

All trademarks and registerd trademarks are property of their respcetive owners.

×
Semiconductor IP